Š žķ;>87„(ŗ7L$Marvell Armada 385 Reference DesignF!marvell,a385-rdmarvell,armada388marvell,armada385marvell,armada380aliases,/soc/internal-regs/gpio@181002/soc/internal-regs/gpio@18140 8/soc/internal-regs/serial@12000 @/soc/internal-regs/serial@12100pmu!arm,cortex-a9-pmuHsoc"!marvell,armada380-mbussimple-bus\gxąŠč@›šń’š ń ńbootrom!marvell,bootrom ¢ devbus-bootcs!marvell,mvebu-devbus ¢š›/’’’’¦ ­disableddevbus-cs0!marvell,mvebu-devbus ¢š›>’’’’¦ ­disableddevbus-cs1!marvell,mvebu-devbus ¢š›=’’’’¦ ­disableddevbus-cs2!marvell,mvebu-devbus ¢š›;’’’’¦ ­disableddevbus-cs3!marvell,mvebu-devbus ¢š ›7’’’’¦ ­disabledinternal-regs !simple-bus›šcache-controller@8000!arm,pl310-cache¢€“ĀĪēscu@c000!arm,cortex-a9-scu¢ĄXtimer@c200!arm,cortex-a9-global-timer¢Ā  " ¦timer@c600!arm,cortex-a9-twd-timer¢Ę  " ¦interrupt-controller@d000!arm,cortex-a9-gic->¢ŠĮSi2c@11000+!marvell,mv78230-a0-i2cmarvell,mv64xxx-i2c¢  "[覭okayf† i2c@11100+!marvell,mv78230-a0-i2cmarvell,mv64xxx-i2c¢  "[č¦ ­disabledserial@12000!marvell,armada-38x-uart¢ v " €¦­okayserial@12100!marvell,armada-38x-uart¢!v " €¦ ­disabledpinctrl@18000¢€ !marvell,mv88f6828-pinctrlge-rgmii-pins-0Dmpp6mpp7mpp8mpp9mpp10mpp11mpp12mpp13mpp14mpp15mpp16mpp17šge0ge-rgmii-pins-1Hmpp21mpp27mpp28mpp29mpp30mpp31mpp32mpp37mpp38mpp39mpp40mpp41šge1i2c-pins-0 mpp2mpp3ši2c0mdio-pins mpp4mpp5šgeref-clk-pins-0mpp45šrefref-clk-pins-1mpp46šrefspi-pins-0mpp22mpp23mpp24mpp25šspi0spi-pins-1mpp56mpp57mpp58mpp59šspi1nand-pinsNmpp22mpp34mpp23mpp33mpp38mpp28mpp40mpp42mpp35mpp36mpp25mpp30mpp32šdevnand-rbmpp41šnanduart-pins-0 mpp0mpp1šua0uart-pins-1 mpp19mpp20šua1sdhci-pins<mpp48mpp49mpp50mpp52mpp53mpp54mpp55mpp57mpp58mpp59šsd0Ssata-pins-0mpp20šsata0sata-pins-1mpp19šsata1sata-pins-2mpp47šsata2sata-pins-3mpp44šsata3gpio@18100+!marvell,armada-370-gpiomarvell,orion-gpio¢@Ą «gpiopwmµ ¼ĢŲ>-0"5678¦gpio@18140+!marvell,armada-370-gpiomarvell,orion-gpio¢@@Č «gpiopwmµ¼ĢŲ>-0":;<=¦system-controller@18200M!marvell,armada-380-system-controllermarvell,armada-370-xp-system-controller¢‚clock-gating-control@18220 !marvell,armada-380-gating-clock¢‚ ¦ćSphy@18300!marvell,armada-380-comphy¢ƒphy@0¢šphy@1¢šphy@2¢šphy@3¢šphy@4¢šphy@5¢šmvebu-sar@18600!marvell,armada-380-core-clock¢†ćSmbus-controller@20000!marvell,mbus-controller¢€ PSinterrupt-controller@20a00 !marvell,mpic¢ ŠpX->ū "Stimer@203001!marvell,armada-380-timermarvell,armada-xp-timer¢0@0PH    ¦  nbclkfixedwatchdog@20300!marvell,armada-380-wdt¢4‚` ¦  nbclkfixed H@ cpurst@20800!marvell,armada-370-cpu-reset¢mpcore-soc-ctrl@20d20#!marvell,armada-380-mpcore-soc-ctrl¢ lcoherency-fabric@21010$!marvell,armada-380-coherency-fabric¢pmsu@22000!marvell,armada-380-pmsu¢ ethernet@70000!marvell,armada-370-neta¢@H¦&H­okay$ (rgmii-idethernet@30000!marvell,armada-370-neta¢@H ¦­okay$ (rgmii-idethernet@34000!marvell,armada-370-neta¢@@H ¦ ­disabledusb@58000!marvell,orion-ehci¢€ "¦ ­disabledxor@60800)!marvell,armada-380-xormarvell,orion-xor¢ ¦­okayxor00 "1?xor01 "1?Jxor@60900)!marvell,armada-380-xormarvell,orion-xor¢  ¦­okayxor10 "A1?xor11 "B1?Jmdio@72004!marvell,orion-mdio¢ ¦ethernet-phy@0¢Sethernet-phy@1¢Scrypto@90000!marvell,armada-38x-crypto¢ «regs" ¦ cesa0cesa1cesaz0cesaz1X mrtc@a3800!marvell,armada-380-rtc¢ 8 „   «rtcrtc-soc "sata@a8000!marvell,armada-380-ahci¢ €  "¦ ­disabledbm@c8000!marvell,armada-380-neta-bm¢ €¬¦ †  ­disabledsata@e0000!marvell,armada-380-ahci¢  "¦ ­disabledclock@e4250!!marvell,armada-380-corediv-clock¢BP ć¦ “nandS thermal@e8078!marvell,armada380-thermal¢@x@p­okaynand-controller@d0000"!marvell,armada370-nand-controller¢ T "T¦  ­disabledsdhci@d8000!marvell,armada-380-sdhci«sdhcimbusconf-sdio3¢ € Ą„T "¦¦­okay¼defaultŹŌŽēóusb3@f0000!marvell,armada-380-xhci¢@@@ "¦ ­okayusb3@f8000!marvell,armada-380-xhci¢€@Ą@ "¦  ­disabledsa-sram0 !mmio-sram ¢ ¦› S sa-sram1 !mmio-sram ¢ ¦› S bm-bppi !mmio-sram ¢ › ¦ ż ­disabledS spi@10600)!marvell,armada-380-spimarvell,orion-spi ¢šP  "¦­okayspi-flash@0!st,m25p128jedec,spi-nor¢oóspi@10680)!marvell,armada-380-spimarvell,orion-spi ¢š€P  "?¦ ­disabledpcie!marvell,armada-370-pcie­okay'pci3>’P›‚š ‚š ‚@š@ ‚€š€ ‚聹‚聹‚ŲŠ‚ø°pcie@1,0'pciH‚ ¢-@›‚‚>’[ n|Ž¦­okaypcie@2,0'pciH‚ ¢-@›‚‚>’[ n!|Ž¦ ­disabledpcie@3,0'pciH‚@ ¢-@›‚‚>’[ nF|Ž¦ ­disabledpcie@4,0'pciH‚€ ¢ -@›‚‚>’[ nG|Ž¦ ­disabledclocksmainpll !fixed-clockćf;šŹS oscillator !fixed-clockćf}x@Scpus marvell,armada-380-smpcpu@0'cpu!arm,cortex-a9¢cpu@1'cpu!arm,cortex-a9¢chosen®serial0:115200n8memory'memory¢ #address-cells#size-cellsmodelcompatiblegpio0gpio1serial0serial1interrupts-extendedcontrollerinterrupt-parentpcie-mem-aperturepcie-io-aperturerangesregclocksstatuscache-unifiedcache-levelarm,double-linefill-incrarm,double-linefill-wraparm,double-linefillprefetch-datainterrupts#interrupt-cellsinterrupt-controllerphandletimeout-msclock-frequencyreg-shiftreg-io-widthmarvell,pinsmarvell,functionreg-namesngpiosgpio-controller#gpio-cells#pwm-cells#clock-cells#phy-cellsmsi-controllerclock-namestx-csum-limitphyphy-modedmacap,memcpydmacap,xordmacap,memsetmarvell,crypto-sramsmarvell,crypto-sram-sizeinternal-memclock-output-namesmrvl,clk-delay-cyclespinctrl-namespinctrl-0broken-cdno-1-8-vwp-invertedbus-widthno-memory-wccell-indexspi-max-frequencydevice_typemsi-parentbus-rangeassigned-addressesinterrupt-map-maskinterrupt-mapmarvell,pcie-portmarvell,pcie-laneenable-methodstdout-path