iU8cx(c@(,chipspark,rayeager-px2rockchip,rk3066a 7Rayeager PX2aliases=/ethernet@10204000G/i2c@2002d000L/i2c@2002f000Q/i2c@20056000V/i2c@2005a000[/i2c@2005e000`/dwmmc@1021c000f/dwmmc@10214000l/dwmmc@10218000r/serial@10124000z/serial@10126000/serial@20064000/serial@20068000/spi@20070000/spi@20074000amba ,simple-busdma-controller@20018000,arm,pl330arm,primecell @ apb_pclkdma-controller@2001c000,arm,pl330arm,primecell @ apb_pclk disableddma-controller@20078000,arm,pl330arm,primecell @ apb_pclkoscillator ,fixed-clockn6 xin24mgpu@10090000",rockchip,rk3066-maliarm,mali-400  corebus*:Ox disabledx5Vgpgpmmupp0ppmmu0pp1ppmmu1pp2ppmmu2pp3ppmmu3fl2-cache-controller@10138000,arm,pl310-cachetHscu@1013c000,arm,cortex-a9-scuglobal-timer@1013c200,arm,cortex-a9-global-timer   local-timer@1013c600,arm,cortex-a9-twd-timer   interrupt-controller@1013d000,arm,cortex-a9-gicserial@10124000&,rockchip,rk3066-uartsnps,dw-apb-uart@ "baudclkapb_pclk@Lokaytxrxdefault serial@10126000&,rockchip,rk3066-uartsnps,dw-apb-uart` #baudclkapb_pclkAM disabledtxrxdefaultqos@1012d000,syscon )qos@1012e000,syscon (qos@1012f000,syscon "qos@1012f080,syscon $qos@1012f100,syscon &qos@1012f180,syscon #qos@1012f200,syscon %qos@1012f280,syscon 'usb@10180000,rockchip,rk3066-usbsnps,dwc2 otgotg @@ *  /usb2-phyokayusb@101c0000 ,snps,dwc2 otghost*  /usb2-phyokaydefault ethernet@10204000,rockchip,rk3066-emac @< 9 D hclkmacrefFdPrmiiokaydefault Y]ethernet-phy@0 hdwmmc@10214000,rockchip,rk2928-dw-mshc!@ Hbiuciurx-txtOQresetokaydefaultdwmmc@10218000,rockchip,rk2928-dw-mshc! Ibiuciurx-txtORresetokaydefault dwmmc@1021c000,rockchip,rk2928-dw-mshc! Jbiuciurx-txtOSresetokaydefault  !!pmu@20004000&,rockchip,rk3066-pmusysconsimple-mfd @reboot-mode,syscon-reboot-mode@RB RBRB )RBpower-controller!,rockchip,rk3066-power-controller5pd_vio@7POI"#$%&'pd_video@6 I(pd_gpu@8I)grf@20008000,syscon  i2c@2002d000,rockchip,rk3066-i2c  (9 i2cPokaydefault*ak8963@d,asahi-kasei,ak8975 +default,mma8452@1d ,fsl,mma8452+default-i2c@2002f000,rockchip,rk3066-i2c  )9 Qi2cokaydefault.tps@2d-/default01P2\2h2t23322 ,ti,tps65910regulatorsregulator@0vcc_rtcvrtcregulator@1vcc_io2Z2Zvio3regulator@2vdd_arm '`vdd1Iregulator@3vcc_ddr '`vdd2regulator@5vcc18w@w@vdig1regulator@6vdd_11vdig2regulator@7vcc_25&%&%vpll?regulator@8 vccio_wlw@w@vdacregulator@9 vcc25_hdmi&%&% vaux1regulator@10vcca_332Z2Z vaux2regulator@11 vcc_rmii2Z2Z vaux33regulator@12 vcc28_cif** vmmcregulator@4vdd3regulator@13 vbbpwm@20030000,rockchip,rk2928-pwm +F disableddefault4pwm@20030010,rockchip,rk2928-pwm +Fokaydefault5watchdog@2004c000 ,rockchip,rk3066-wdtsnps,dw-wdt K 3okaypwm@20050020,rockchip,rk2928-pwm  +Gokaydefault6pwm@20050030,rockchip,rk2928-pwm 0+Gokaydefault7Zi2c@20056000,rockchip,rk3066-i2c ` *9 Ri2cokaydefault8i2c@2005a000,rockchip,rk3066-i2c  +9 Si2cokaydefault9i2c@2005e000,rockchip,rk3066-i2c  49 Ti2cokaydefault:serial@20064000&,rockchip,rk3066-uartsnps,dw-apb-uart @ $baudclkapb_pclkBNokaytxrxdefault;serial@20068000&,rockchip,rk3066-uartsnps,dw-apb-uart  %baudclkapb_pclkCOokay txrxdefault <=>saradc@2006c000,rockchip,saradc  6GJsaradcapb_pclkOW saradc-apbokayH?spi@20070000,rockchip,rk3066-spiEHspiclkapb_pclk &   txrxokaydefault@ABCspi@20074000,rockchip,rk3066-spiFIspiclkapb_pclk ' @  txrx disableddefaultDEFGcpusTrockchip,rk3066-smpcpu@0bcpu,arm,cortex-a9nH8@ Oa* s* 'g8@Icpu@1bcpu,arm,cortex-a9nHdisplay-subsystem,rockchip,display-subsystemJKsram@10080000 ,mmio-sram smp-sram@0,rockchip,rk3066-smp-sramPvop@1010c000,rockchip,rk3066-vop aclk_vopdclk_vophclk_vopfOdef axiahbdclk disabledportJendpoint@0LPvop@1010e000,rockchip,rk3066-vop aclk_vopdclk_vophclk_vopfOghi axiahbdclk disabledportKendpoint@0MQhdmi@10116000,rockchip,rk3066-hdmi`  @hclkdefaultNOf9  disabledportsport@0endpoint@0PLendpoint@1QMport@1i2s@10118000,rockchip,rk3066-i2s  defaultRtxrxi2s_hclki2s_clkK disabledi2s@1011a000,rockchip,rk3066-i2s  defaultStxrxi2s_hclki2s_clkL disabledi2s@1011c000,rockchip,rk3066-i2s  defaultT  txrxi2s_hclki2s_clkM disabledclock-controller@20000000,rockchip,rk3066a-cru 9  @*^_ :ׄ#gрxhрxhtimer@2000e000,snps,dw-apb-timer-osc  .VD timerpclkefuse@20010000,rockchip,rk3066a-efuse @[ pclk_efusecpu_leakage@17timer@20038000,snps,dw-apb-timer-osc  ,TB timerpclktimer@2003a000,snps,dw-apb-timer-osc  -UC timerpclktsadc@20060000,rockchip,rk3066-tsadc ]]saradcapb_pclk 6O\ saradc-apb disabledphy1,rockchip,rk3066a-usb-phyrockchip,rk3288-usb-phy9 okayusb-phy@17c|Qphyclk  usb-phy@188Rphyclk  pinctrl,rockchip,rk3066a-pinctrl9 gpio0@20034000,rockchip,gpio-bank @ 6U._gpio1@2003c000,rockchip,gpio-bank  7V.gpio2@2003e000,rockchip,gpio-bank  8W.gpio3@20080000,rockchip,gpio-bank  9X.]gpio4@20084000,rockchip,gpio-bank @ :Y.+gpio6@2000a000,rockchip,gpio-bank  <Z./pcfg_pull_default:Wpcfg_pull_nonePUemacemac-xfer]UUUUUUUUemac-mdio ]UUrmii-rst]Vemmcemmc-clk]Wemmc-cmd] Wemmc-rst] W hdmihdmi-hpd]WOhdmii2c-xfer ]UUNi2c0i2c0-xfer ]UU*i2c1i2c1-xfer ]UU.i2c2i2c2-xfer ]UU8i2c3i2c3-xfer ]UU9i2c4i2c4-xfer ]UU:pwm0pwm0-out]U4pwm1pwm1-out]U5pwm2pwm2-out]U6pwm3pwm3-out]U7spi0spi0-clk]W@spi0-cs0]WCspi0-tx]WAspi0-rx]WBspi0-cs1]Wspi1spi1-clk]WDspi1-cs0]WGspi1-rx]WFspi1-tx]WEspi1-cs1]Wuart0uart0-xfer ]WWuart0-cts]Wuart0-rts]Wuart1uart1-xfer ]WWuart1-cts]Wuart1-rts]Wuart2uart2-xfer ]W W;uart3uart3-xfer ]WW<uart3-cts]W=uart3-rts]W>sd0sd0-clk]Wsd0-cmd] Wsd0-cd]Wsd0-wp]Wsd0-bus-width1] Wsd0-bus-width4@] W W W Wsd1sd1-clk]Wsd1-cmd]Wsd1-cd]Wsd1-wp]Wsd1-bus-width1]Wsd1-bus-width4@]WWWWi2s0i2s0-bus]WW W W W W WWWRi2s1i2s1-bus`]WWWWWWSi2s2i2s2-bus`]WWWWWWTpcfg-output-highkVak8963comp-int]W,irir-int]WXkeyspwr-key]WYmma8452gsensor-int]W-mmcsdmmc-pwr]W^usb_hosthost-drv]W`hub-rst]V sata-pwr]W[sata-reset] V usb_otgotg-drv]Watpspmic-int]W0pwr-hold]V1memory@60000000bmemory`@ir-receiver,gpio-ir-receiver n/defaultXgpio-keys ,gpio-keyspowerw n/ GPIO PowertdefaultYvdd-log,pwm-regulator Zvdd_logOOB@dO*okayvsys-regulator,regulator-fixedvsysLK@LK@25v-stdby-regulator,regulator-fixed 5v_stdbyLK@LK@\emmc-regulator,regulator-fixed emmc_vccq--2!sata-regulator,regulator-fixed +default[usb_5vLK@LK@\sdmmc-regulator,regulator-fixed ]default^vcc_sd2Z2Z3usb-host-regulator,regulator-fixed _default` host-pwrLK@LK@\usb-otg-regulator,regulator-fixed _defaultavcc_otgLK@LK@\ #address-cells#size-cellsinterrupt-parentcompatiblemodelethernet0i2c0i2c1i2c2i2c3i2c4mshc0mshc1mshc2serial0serial1serial2serial3spi0spi1rangesreginterrupts#dma-cellsarm,pl330-broken-no-flushpclocksclock-namesphandlestatusclock-frequency#clock-cellsclock-output-namesassigned-clocksassigned-clock-ratesresetsinterrupt-namespower-domainscache-unifiedcache-levelinterrupt-controller#interrupt-cellsreg-shiftreg-io-widthdmasdma-namespinctrl-namespinctrl-0dr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephysphy-namesrockchip,grfmax-speedphy-modephyphy-supplyreset-gpiosfifo-depthreset-namesmax-frequencybus-widthdisable-wpvmmc-supplycap-mmc-highspeedcap-sd-highspeednon-removablevqmmc-supplyoffsetmode-normalmode-recoverymode-bootloadermode-loader#power-domain-cellspm_qosvcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvccio-supplyregulator-nameregulator-always-onregulator-compatibleregulator-min-microvoltregulator-max-microvoltregulator-boot-on#pwm-cells#io-channel-cellsvref-supplyenable-methoddevice_typenext-level-cacheoperating-pointsclock-latencycpu0-supplyportsremote-endpointrockchip,playback-channelsrockchip,capture-channels#sound-dai-cells#reset-cells#phy-cellsgpio-controller#gpio-cellsbias-pull-pin-defaultbias-disablerockchip,pinsoutput-highwakeup-sourcelabellinux,codepwmsvoltage-tablevin-supplyenable-active-highgpiostartup-delay-us