T8OL(`O!,Rockchip RK3228 Evaluation board$2rockchip,rk3228-evbrockchip,rk3228aliases=/serial@11010000E/serial@11020000M/serial@11030000U/spi@11090000cpuscpu@f00Zcpu2arm,cortex-a7fjq@pscicpu@f01Zcpu2arm,cortex-a7fjqpscicpu@f02Zcpu2arm,cortex-a7fjqpscicpu@f03Zcpu2arm,cortex-a7fjqpsciopp_table02operating-points-v2opp-408000000Q~@opp-600000000#Fopp-8160000000,B@opp-1008000000<opp-1200000000Gtxamba 2simple-buspdma@110f00002arm,pl330arm,primecellf@ apb_pclk arm-pmu2arm,cortex-a7-pmu0LMNO%psci2arm,psci-1.0arm,psci-0.2smctimer2arm,armv7-timer80   \n6oscillator 2fixed-clock\n6lxin24mdisplay-subsystem2rockchip,display-subsystemi2s1@100b0000(2rockchip,rk3228-i2srockchip,rk3066-i2sf @ i2s_clki2s_hclkQ  txrxdefault  disabledi2s0@100c0000(2rockchip,rk3228-i2srockchip,rk3066-i2sf @ i2s_clki2s_hclkP txrx disabledspdif@100d00002rockchip,rk3228-spdiff  S mclkhclk txdefault  disabledi2s2@100e0000(2rockchip,rk3228-i2srockchip,rk3066-i2sf@ i2s_clki2s_hclkR txrx disabledsyscon@11000000&2rockchip,rk3228-grfsysconsimple-mfdfio-domains"2rockchip,rk3228-io-voltage-domain disabledusb2-phy@7602rockchip,rk3228-usb2phyf` phyclk lusb480m_phy0 disabled6otg-port$;<=otg-bvalidotg-idlinestate disabled5host-port > linestate disabled7usb2-phy@8002rockchip,rk3228-usb2phyf phyclk lusb480m_phy1 disabled8otg-port D linestate disabled9host-port E linestate disabled:serial@110100002snps,dw-apb-uartf 7\n6MUbaudclkapb_pclkdefault   disabledserial@110200002snps,dw-apb-uartf 8\n6NVbaudclkapb_pclkdefault disabledserial@110300002snps,dw-apb-uartf 9\n6OWbaudclkapb_pclkdefaultokayefuse@110400002rockchip,rk3228-efusef G pclk_efuseid@7fcpu_leakage@17fi2c@110500002rockchip,rk3228-i2cf $i2cLdefault disabledi2c@110600002rockchip,rk3228-i2cf %i2cMdefault disabledi2c@110700002rockchip,rk3228-i2cf &i2cNdefault disabledi2c@110800002rockchip,rk3228-i2cf 'i2cOdefault disabledspi@110900002rockchip,rk3228-spif  1ARspiclkapb_pclkdefault disabledwatchdog@110a0000 2snps,dw-wdtf  (b disabledpwm@110b00002rockchip,rk3288-pwmf ^pwmdefault disabledpwm@110b00102rockchip,rk3288-pwmf ^pwmdefault disabledpwm@110b00202rockchip,rk3288-pwmf ^pwmdefault disabledpwm@110b00302rockchip,rk3288-pwmf 0^pwmdefault disabledtimer@110c0000,2rockchip,rk3228-timerrockchip,rk3288-timerf  + a timerpclkclock-controller@110e00002rockchip,rk3228-cruf Hkb$'#g0,eррxhррxhthermal-zonescpu-thermal<dR` tripscpu_alert0pp|apassive!cpu_alert1p$|apassive"cpu_critp_| acriticalcooling-mapsmap0!0map1"0tsadc@111500002rockchip,rk3228-tsadcf :HXtsadcapb_pclkH'jW tsadc-apbinitdefaultsleep#$#sokay hdmi-phy@120300002rockchip,rk3228-hdmi-phyfmsysclkrefoclkrefpclk lhdmiphy_phy disabled'gpu@20000000"2rockchip,rk3228-maliarm,mali-400f Hgpgpmmupp0ppmmu0pp1ppmmu1 corebusj~ disablediommu@200208002rockchip,iommuf   vpu_mmu aclkiface disablediommu@200304802rockchip,iommuf @ @  vdec_mmu aclkiface disabledvop@200500002rockchip,rk3228-vopf   aclk_vopdclk_vophclk_vopjdef axiahbdclk&% disabledportendpoint@0f-&+iommu@20053f002rockchip,iommuf ?  vop_mmu aclkiface= disabled%iommu@200708002rockchip,iommuf  iep_mmu aclkiface disabledhdmi@200a00002rockchip,rk3228-dw-hdmif  #J'{lisfriahbcecdefault ()*j`hdmia'fhdmi disabledportsportendpoint@0f-+&dwmmc@3000000002rockchip,rk3228-dw-mshcrockchip,rk3288-dw-mshcf0@   Drvbiuciuciu-driveciu-samplepdefault ,-. disableddwmmc@3001000002rockchip,rk3228-dw-mshcrockchip,rk3288-dw-mshcf0@   Eswbiuciuciu-driveciu-samplepdefault /01 disableddwmmc@3002000002rockchip,rk3228-dw-mshcrockchip,rk3288-dw-mshcf0@ \<4`{<4` Guybiuciuciu-driveciu-samplepdefault 234jSresetokayusb@3004000022rockchip,rk3228-usbrockchip,rk3066-usbsnps,dwc2f0 otgotg @ a5 fusb2-phy disabledusb@30080000 2generic-ehcif0  6 usbhostutmia7fusb disabledusb@300a0000 2generic-ohcif0   6 usbhostutmia7fusb disabledusb@300c0000 2generic-ehcif0   8 usbhostutmia9fusb disabledusb@300e0000 2generic-ohcif0  8 usbhostutmia9fusb disabledusb@30100000 2generic-ehcif0 B 8a:fusb usbhostutmi disabledusb@30120000 2generic-ohcif0 C 8 usbhostutmia:fusb disabledethernet@302000002rockchip,rk3228-gmacf0  macirq8~oMstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macj8 stmmacethokay|'"output/;:rmiiC<mdio2snps,dwmac-mdiophy@042ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22fj?N<interrupt-controller@32010000 2arm,gic-400`u f22 2@ 2`   pinctrl2rockchip,rk3228-pinctrlgpio0@111100002rockchip,gpio-bankf 3@`ugpio1@111200002rockchip,gpio-bankf 4A`ugpio2@111300002rockchip,gpio-bankf 5B`ugpio3@111400002rockchip,gpio-bankf 6C`upcfg-pull-up@pcfg-pull-down?pcfg-pull-none>pcfg-pull-none-drv-12ma =sdmmcsdmmc-clk=,sdmmc-cmd=-sdmmc-bus4@====.sdiosdio-clk=/sdio-cmd=0sdio-bus4@====1emmcemmc-clk>2emmc-cmd>3emmc-bus8>>>>>>>>4gmacrgmii-pins> >>==== = =>>>> >>rmii-pins> >>== =>>>>phy-pins >>hdmihdmi-hpd?)hdmii2c-xfer >>(hdmi-cec>*i2c0i2c0-xfer >>i2c1i2c1-xfer >>i2c2i2c2-xfer >>i2c3i2c3-xfer >>spi-0spi0-clk @spi0-cs0@spi0-tx @spi0-rx @spi0-cs1 @spi-1spi1-clk@spi1-cs0@spi1-rx@spi1-tx@spi1-cs1@i2s1i2s1-bus> > > > >>>>> pwm0pwm0-pin>pwm1pwm1-pin>pwm2pwm2-pin >pwm3pwm3-pin >spdifspdif-tx> tsadcotp-gpio>#otp-out>$uart0uart0-xfer >> uart0-cts> uart0-rts>uart1uart1-xfer  > >uart1-cts>uart1-rts >uart2uart2-xfer @>uart21-xfer  @ >uart2-cts>uart2-rts>memory@60000000Zmemoryf`@vcc-phy-regulator2regulator-fixedvcc_phy w@"w@:N; #address-cells#size-cellsinterrupt-parentmodelcompatibleserial0serial1serial2spi0device_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksenable-methodphandleopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendrangesinterrupts#dma-cellsclock-namesinterrupt-affinityarm,cpu-registers-not-fw-configuredclock-frequencyclock-output-names#clock-cellsportsdmasdma-namespinctrl-namespinctrl-0statusinterrupt-names#phy-cellsreg-shiftreg-io-width#pwm-cellsrockchip,grf#reset-cellsassigned-clocksassigned-clock-ratespolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicereset-namespinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityiommu-cellsiommusremote-endpoint#iommu-cellsassigned-clock-parentsphysphy-namesfifo-depthmax-frequencybus-widthdefault-sample-phasecap-mmc-highspeedmmc-ddr-1_8vdisable-wpnon-removabledr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeg-use-dmaclock_in_outphy-supplyphy-modephy-handlephy-is-integratedinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthrockchip,pinsenable-active-highregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-on