8( Tgoogle,veyron-mickey-rev8google,veyron-mickey-rev7google,veyron-mickey-rev6google,veyron-mickey-rev5google,veyron-mickey-rev4google,veyron-mickey-rev3google,veyron-mickey-rev2google,veyron-mickey-rev1google,veyron-mickey-rev0google,veyron-mickeygoogle,veyronrockchip,rk3288&7Google Mickeyaliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/dwmmc@ff0f0000k/dwmmc@ff0c0000q/dwmmc@ff0d0000w/dwmmc@ff0e0000}/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000arm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12'@5<rV bcpu@501cpuarm,cortex-a12'@5<rbcpu@502cpuarm,cortex-a12'@5<rbcpu@503cpuarm,cortex-a12'@5<rbcpu-opp-tableoperating-points-v2jbopp-126000000u| opp-216000000u | opp-408000000uQ| opp-600000000u#F| opp-696000000u)||~opp-816000000u0,|B@opp-1008000000u<|opp-1200000000uG|opp-1416000000uTfr|Oopp-1512000000uZJ|opp-1608000000u_"| opp-1704000000ue|popp-1800000000ukI|\amba simple-busdma-controller@ff250000arm,pl330arm,primecell%@5 apb_pclkbdma-controller@ff600000arm,pl330arm,primecell`@5 apb_pclk disableddma-controller@ffb20000arm,pl330arm,primecell@5 apb_pclkb[reserved-memorydma-unusable@fe000000oscillator fixed-clockn6xin24mb timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer  H 5 a timerpclkdisplay-subsystemrockchip,display-subsystem5 dwmmc@ff0c0000rockchip,rk3288-dw-mshc;р 5Drvbiuciuciu-driveciu-sampleI  @Treset disableddwmmc@ff0d0000rockchip,rk3288-dw-mshc;р 5Eswbiuciuciu-driveciu-sampleI ! @Tresetokay`j{ default dwmmc@ff0e0000rockchip,rk3288-dw-mshc;р 5Ftxbiuciuciu-driveciu-sampleI "@Treset disableddwmmc@ff0f0000rockchip,rk3288-dw-mshc;р 5Guybiuciuciu-driveciu-sampleI #@Tresetokay`/MXdefault saradc@ff100000rockchip,saradc $g5I[saradcapb_pclkW Tsaradc-apb disabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi5ARspiclkapb_pclky  ~txrx ,default disabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi5BSspiclkapb_pclky ~txrx -default disabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi5CTspiclkapb_pclky~txrx .default !"#okay flash@0jedec,spi-nori2c@ff140000rockchip,rk3288-i2c >i2c5Mdefault$okay2dtpm@20infineon,slb9645tt i2c@ff150000rockchip,rk3288-i2c ?i2c5Odefault% disabledi2c@ff160000rockchip,rk3288-i2c @i2c5Pdefault& disabled2,i2c@ff170000rockchip,rk3288-i2c Ai2c5Qdefault' disabledserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 75MUbaudclkapb_pclkdefault ()*okayserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 85NVbaudclkapb_pclkdefault+okayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 95OWbaudclkapb_pclkdefault,okayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart :5PXbaudclkapb_pclkdefault- disabledserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ;5QYbaudclkapb_pclkdefault. disabledthermal-zonesreserve_thermal !//cpu_thermal d!//tripscpu_crit?_K criticalcpu_alert_almost_warm?Kpassivecpu_alert_warm?Kpassiveb0cpu_alert_almost_hot?8Kpassiveb2cpu_alert_hot?@PKpassiveb3cpu_alert_hotter?H Kpassiveb4cpu_alert_very_hot?LKpassiveb5cooling-mapscpu_warm_limit_cpuV00[cpu_warm_limit_gpuV0 [1cpu_almost_hot_limit_cpuV20[cpu_hot_limit_cpuV30[cpu_hotter_limit_cpuV40[cpu_very_hot_limit_cpuV50[cpu_very_hot_limit_gpuV5 [1gpu_thermal d!//tripsgpu_crit?_K criticalgpu_alert_warmish?`Kpassiveb6gpu_alert_warm?Kpassiveb7gpu_alert_hotter?H Kpassiveb8gpu_alert_very_very_hot?OKpassiveb9cooling-mapsgpu_warmish_limit_gpuV6 [1gpu_warm_limit_cpuV70[gpu_hotter_limit_gpuV8 [1gpu_very_very_hot_limit_gpuV9 [1tsadc@ff280000rockchip,rk3288-tsadc( %5HZtsadcapb_pclk Ttsadc-apbinitdefaultsleep:j;t:~<Hokayb/ethernet@ff290000rockchip,rk3288-gmac)macirqeth_wake_irq<85fgc]Mstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macB Tstmmaceth disabledusb@ff500000 generic-ehciP 5usbhost=usb disabled usb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T 5otghost> usb2-phy' disabled>usb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X 5otghostUgv@@ ? usb2-phyokayz?>usb@ff5c0000 generic-ehci\ 5usbhost disabledi2c@ff650000rockchip,rk3288-i2ce <i2c5Ldefault@okay2dpmic@1brockchip,rk808xin32kwifibt_32kin&Adefault BCD #E0F F:bregulatorsDCDC_REG1Gvdd_armVj| q qb regulator-state-memDCDC_REG2Gvdd_gpuVj| 5qbwregulator-state-memDCDC_REG3 Gvcc135_ddrVjregulator-state-memDCDC_REG4Gvcc_18Vj|w@w@bregulator-state-memw@LDO_REG3Gvdd_10Vj|B@B@regulator-state-memB@LDO_REG7 Gvdd10_lcdVj|B@B@SWITCH_REG1 Gvcc33_lcdVjbZregulator-state-memLDO_REG8Vj|w@w@ Gvcc18_lcdi2c@ff660000rockchip,rk3288-i2cf =i2c5NdefaultG disabled2 pwm@ff680000rockchip,rk3288-pwmh-defaultH5_pwm disabledpwm@ff680010rockchip,rk3288-pwmh-defaultI5_pwmokaybpwm@ff680020rockchip,rk3288-pwmh -defaultJ5_pwm disabledpwm@ff680030rockchip,rk3288-pwmh0-defaultK5_pwm disabledbus_intmem@ff700000 mmio-sramppsmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdsbpower-controller!rockchip,rk3288-power-controller8h b^pd_vio@9 5chgfdehilkj$LLMNOPQRSTpd_hevc@11 5opLUVpd_video@12 5LWpd_gpu@13 5LXYreboot-modesyscon-reboot-modeSZRBfRBtRB RBsyscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruv<Hjk$#gׄeрxhрxhbsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfdwb<edp-phyrockchip,rk3288-dp-phy5h24m disabledbnio-domains"rockchip,rk3288-io-voltage-domainokayEEEZ usbphyrockchip,rk3288-usb-phyokayusb-phy@320 5]phyclk Tphy-resetb?usb-phy@33445^phyclk Tphy-resetb=usb-phy@348H5_phyclk Tphy-resetb>watchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt5p Ookaysound@ff88b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif hclkmclk5Ty[~tx 6default\< disabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s 5y[[~txrxi2s_hclki2s_clk5Rdefault]'Bokaycypto-controller@ff8a0000rockchip,rk3288-crypto@ 0 5}aclkhclksclkapb_pclk Tcrypto-rstokayiommu@ff900800rockchip,iommu@ iep_mmu5 aclkiface\ disablediommu@ff914000rockchip,iommu @P isp_mmu5 aclkiface\i disabledrga@ff920000rockchip,rk3288-rga 5jaclkhclksclk^ ilm Tcoreaxiahbvop@ff930000rockchip,rk3288-vop 5aclk_vopdclk_vophclk_vop^ def Taxiahbdclk_okayportb endpoint@0`bsendpoint@1aboendpoint@2bbiendpoint@3cbliommu@ff930300rockchip,iommu  vopb_mmu5 aclkiface^ \okayb_vop@ff940000rockchip,rk3288-vop 5aclk_vopdclk_vophclk_vop^  Taxiahbdclkd disabledportb endpoint@0ebtendpoint@1fbpendpoint@2gbjendpoint@3hbmiommu@ff940300rockchip,iommu  vopl_mmu5 aclkiface^ \ disabledbdmipi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi@ 5~d refpclk^ < disabledportsportendpoint@0ibbendpoint@1jbglvds@ff96c000rockchip,rk3288-lvds@5g pclk_lvdslcdck^ < disabledportsport@0endpoint@0lbcendpoint@1mbhdp@ff970000rockchip,rk3288-dp@ b5icdppclkndpoTdp< disabledportsport@0endpoint@0obaendpoint@1pbfhdmi@ff980000rockchip,rk3288-dw-hdmi< g5hmniahbisfrcec^ okaydefaultunwedgeqjrportsportendpoint@0sb`endpoint@1tbevideo-codec@ff9a0000rockchip,rk3288-vpu   vepuvdpu5 aclkhclku^ iommu@ff9a0800rockchip,iommu vpu_mmu5 aclkiface\^ buiommu@ff9c0440rockchip,iommu @@@ o hevc_mmu5 aclkiface\ disabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760$ jobmmugpu5v^ okaywb1gpu-opp-tableoperating-points-v2bvopp-100000000u|~opp-200000000u |~opp-300000000u|B@opp-400000000uׄ|opp-600000000u#F|qos@ffaa0000syscon bXqos@ffaa0080syscon bYqos@ffad0000syscon bMqos@ffad0100syscon bNqos@ffad0180syscon bOqos@ffad0400syscon bPqos@ffad0480syscon bQqos@ffad0500syscon bLqos@ffad0800syscon bRqos@ffad0880syscon bSqos@ffad0900syscon bTqos@ffae0000syscon bWqos@ffaf0000syscon bUqos@ffaf0080syscon bVefuse@ffb40000rockchip,rk3288-efuse 5q pclk_efusecpu_leakage@17interrupt-controller@ffc01000 arm,gic-400@ @ `   bpinctrlrockchip,rk3288-pinctrl<defaultsleepxyz{jxyz|gpio0@ff750000rockchip,gpio-banku Q5@|PMIC_SLEEP_APPMIC_INT_LPOWER_BUTTON_LRECOVERY_SW_LOT_RESETAP_WARM_RESET_HI2C0_SDA_PMICI2C0_SCL_PMICnFALUTbAgpio1@ff780000rockchip,gpio-bankx R5Agpio2@ff790000rockchip,gpio-banky S5B0CONFIG0CONFIG1CONFIG2CONFIG3EMMC_RST_Lbgpio3@ff7a0000rockchip,gpio-bankz T5CFLASH0_D0FLASH0_D1FLASH0_D2FLASH0_D3FLASH0_D4FLASH0_D5FLASH0_D6FLASH0_D7FLASH0_CS2/EMMC_CMDFLASH0_DQS/EMMC_CLKOgpio4@ff7b0000rockchip,gpio-bank{ U5DUART0_RXDUART0_TXDUART0_CTS_LUART0_RTS_LSDIO0_D0SDIO0_D1SDIO0_D2SDIO0_D3SDIO0_CMDSDIO0_CLKBT_DEV_WAKEWIFI_ENABLE_HBT_ENABLE_LWIFI_HOST_WAKEBT_HOST_WAKEbgpio5@ff7c0000rockchip,gpio-bank| V5Egpio6@ff7d0000rockchip,gpio-bank} W5Fgpio7@ff7e0000rockchip,gpio-bank~ X5GPWM_LOGTPM_INT_HSDMMC_DET_LAP_FLASH_WP_LCPU_NMIDVSOKHDMI_WAKEPOWER_HDMI_ONDVS1DVS2HDMI_CECI2C5_SDA_HDMII2C5_SCL_HDMIUART2_RXDUART2_TXDbFgpio8@ff7f0000rockchip,gpio-bank Y5H^RAM_ID0RAM_ID1RAM_ID2RAM_ID3I2C1_SDA_TPMI2C1_SCL_TPMSPI2_CLKSPI2_CS0SPI2_RXDSPI2_TXDhdmihdmi-cec-c0 }hdmi-cec-c7 }hdmi-ddc }}bqhdmi-ddc-unwedge ~}brpower-hdmi-on  }bpcfg-output-low b~pcfg-pull-up bpcfg-pull-down -bpcfg-pull-none <b}pcfg-pull-none-12ma < I bsleepglobal-pwroff }bzddrio-pwroff }byddr0-retention bxddr1-retention edpedp-hpd  i2c0i2c0-xfer }}b@i2c1i2c1-xfer }}b$i2c2i2c2-xfer  } }bGi2c3i2c3-xfer }}b%i2c4i2c4-xfer }}b&i2c5i2c5-xfer }}b'i2s0i2s0-bus` }}}}}}b]lcdclcdc-ctl@ }}}}bksdmmcsdmmc-clk }sdmmc-cmd sdmmc-cd sdmmc-bus1 sdmmc-bus4@ sdio0sdio0-bus1 sdio0-bus4@ bsdio0-cmd bsdio0-clk bsdio0-cd sdio0-wp sdio0-pwr sdio0-bkpwr sdio0-int wifienable-h }bbt-enable-l }bbt-host-wake bbt-dev-wake-sleep ~b|bt-dev-wake-awake b{sdio1sdio1-bus1 sdio1-bus4@ sdio1-cd sdio1-wp sdio1-bkpwr sdio1-int sdio1-cmd sdio1-clk }sdio1-pwr  emmcemmc-clk bemmc-cmd bemmc-pwr  emmc-bus1 emmc-bus4@ emmc-bus8 bemmc-reset  }bspi0spi0-clk  bspi0-cs0  bspi0-tx bspi0-rx bspi0-cs1 spi1spi1-clk  bspi1-cs0  bspi1-rx bspi1-tx bspi2spi2-cs1 spi2-clk b spi2-cs0 b#spi2-rx b"spi2-tx  b!uart0uart0-xfer }b(uart0-cts b)uart0-rts }b*uart1uart1-xfer  }b+uart1-cts  uart1-rts  }uart2uart2-xfer }b,uart3uart3-xfer }b-uart3-cts  uart3-rts  }uart4uart4-xfer }b.uart4-cts  uart4-rts  }tsadcotp-gpio  }b:otp-out  }b;pwm0pwm0-pin }bHpwm1pwm1-pin }bIpwm2pwm2-pin }bJpwm3pwm3-pin }bKgmacrgmii-pins }}}}}}} }}rmii-pins }}}}}}}}}}spdifspdif-tx  }b\pcfg-pull-none-drv-8ma < Ibpcfg-pull-up-drv-8ma  Ipcfg-output-high Xbbuttonspwr-key-l bpmicpmic-int-l bBdvs-1  bCdvs-2 bDrebootap-warm-reset-h  }brecovery-switchrec-mode-l  tpmtpm-int-h }write-protectfw-wp-ap }chosen dserial2:115200n8memorymemorybt-activity gpio-keysdefaultbt-wake pBT Wakeup 4 vpower-button gpio-keysdefaultpower pPower 4A vt dgpio-restart gpio-restart 4A default emmc-pwrseqmmc-pwrseq-emmcdefault bsdio-pwrseqmmc-pwrseq-simple5 ext_clockdefault b vcc-5vregulator-fixedGvcc_5vVj|LK@LK@ bvcc33-sysregulator-fixed Gvcc33_sysVj|2Z2Zbvcc50-hdmiregulator-fixed Gvcc50_hdmiVj   F defaultvdd-logicpwm-regulator Gvdd_logic   { Vj|~pvcc33_ioregulator-fixed Gvcc33_ioVj bE #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksdynamic-power-coefficientcpu0-supplyphandleopp-sharedopp-hzopp-microvoltranges#dma-cellsarm,pl330-broken-no-flushpclock-namesstatusclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendportsmax-frequencyfifo-depthreset-namesbus-widthcap-sd-highspeedcap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablepinctrl-namespinctrl-0sd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplycap-mmc-highspeedrockchip,default-sample-phasedisable-wpmmc-hs200-1_8v#io-channel-cellsdmasdma-namesrx-sample-delay-nsspi-max-frequencyi2c-scl-falling-time-nsi2c-scl-rising-time-nspowered-while-suspendedreg-shiftreg-io-widthpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesphysphy-namesneeds-reset-on-resumedr_modesnps,reset-phy-on-wakesnps,need-phy-for-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeassigned-clocksassigned-clock-parentsrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc7-supplyvcc8-supplyvddio-supplydvs-gpiosvcc11-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvoltregulator-suspend-mem-disabled#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsbb-supplydvp-supplyflash0-supplygpio1830-supplygpio30-supplylcdc-supplywifi-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointmali-supplyinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsgpio-line-namesrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highstdout-pathlabellinux,codedebounce-intervalpriorityreset-gpiosvin-supplyenable-active-highgpiopwmspwm-supplypwm-dutycycle-rangepwm-dutycycle-unit