8( 6lgoogle,veyron-mighty-rev5google,veyron-mighty-rev4google,veyron-mighty-rev3google,veyron-mighty-rev2google,veyron-mighty-rev1google,veyron-mightygoogle,veyronrockchip,rk3288&7Google Mightyaliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/dwmmc@ff0f0000k/dwmmc@ff0c0000q/dwmmc@ff0d0000w/dwmmc@ff0e0000}/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000/spi@ff110000/ec@0/i2c-tunnelarm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12 -@;Br\ hcpu@501cpuarm,cortex-a12 -@;Brhcpu@502cpuarm,cortex-a12 -@;Brhcpu@503cpuarm,cortex-a12 -@;Brhcpu-opp-tableoperating-points-v2phopp-126000000{ opp-216000000{  opp-408000000{Q opp-600000000{#F opp-696000000{)|~opp-816000000{0,B@opp-1008000000{<opp-1200000000{Gopp-1416000000{TfrOopp-1512000000{ZJopp-1608000000{_" opp-1704000000{epopp-1800000000{kI\amba simple-busdma-controller@ff250000arm,pl330arm,primecell%@; apb_pclkh dma-controller@ff600000arm,pl330arm,primecell`@; apb_pclk disableddma-controller@ffb20000arm,pl330arm,primecell@; apb_pclkhdreserved-memorydma-unusable@fe000000oscillator fixed-clockn6xin24mh timerarm,armv7-timer0   n6$timer@ff810000rockchip,rk3288-timer  H ; a timerpclkdisplay-subsystemrockchip,display-subsystem; dwmmc@ff0c0000rockchip,rk3288-dw-mshcAр ;Drvbiuciuciu-driveciu-sampleO  @Zresetokayfp  Z default( 2 dwmmc@ff0d0000rockchip,rk3288-dw-mshcAр ;Eswbiuciuciu-driveciu-sampleO ! @Zresetokayf;H^idefault ( dwmmc@ff0e0000rockchip,rk3288-dw-mshcAр ;Ftxbiuciuciu-driveciu-sampleO "@Zreset disableddwmmc@ff0f0000rockchip,rk3288-dw-mshcAр ;Guybiuciuciu-driveciu-sampleO #@Zresetokayfpw^idefault (saradc@ff100000rockchip,saradc $;I[saradcapb_pclkW Zsaradc-apb disabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi;ARspiclkapb_pclk txrx ,default(!"#$okayec@0google,cros-ec-spi& default(%-i2c-tunnelgoogle,cros-ec-i2c-tunnelsbs-battery@bsbs,sbs-battery keyboard-controllergoogle,cros-ec-keyb, ?@Y};0DY1 d>"A#( C  \=@V B |)<?   + ^a !%$' & + ,./-32*5 4 9    8 l j6  g ispi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi;BSspiclkapb_pclk txrx -default(&'() disabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi;CTspiclkapb_pclk  txrx .default(*+,-okayf flash@0jedec,spi-nori2c@ff140000rockchip,rk3288-i2c >i2c;Mdefault(.okayy2dtpm@20infineon,slb9645tt i2c@ff150000rockchip,rk3288-i2c ?i2c;Odefault(/ disabledi2c@ff160000rockchip,rk3288-i2c @i2c;Pdefault(0okayy2,ts3a227e@3b ti,ts3a227e;&1default(2htrackpad@15elan,ekth3000& default(34i2c@ff170000rockchip,rk3288-i2c Ai2c;Qdefault(5 disabledserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 7;MUbaudclkapb_pclkdefault (678okayserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 8;NVbaudclkapb_pclkdefault(9okayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 9;OWbaudclkapb_pclkdefault(:okayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart :;PXbaudclkapb_pclkdefault(; disabledserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ;;QYbaudclkapb_pclkdefault(< disabledthermal-zonesreserve_thermal=cpu_thermald=tripscpu_alert0/p;passiveh>cpu_alert1/$;passiveh?cpu_crit/; criticalcooling-mapsmap0F>0Kmap1F?0Kgpu_thermald=tripsgpu_alert0/4;passiveh@gpu_crit/; criticalcooling-mapsmap0F@ KAtsadc@ff280000rockchip,rk3288-tsadc( %;HZtsadcapb_pclk Ztsadc-apbinitdefaultsleep(BZCdBnDHokayh=ethernet@ff290000rockchip,rk3288-gmac)macirqeth_wake_irqD8;fgc]Mstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macB Zstmmaceth disabledusb@ff500000 generic-ehciP ;usbhostEusbokayusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T ;otghostF usb2-phyokay.usb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X ;otghostEWf@@ G usb2-phyokayuzG.usb@ff5c0000 generic-ehci\ ;usbhost disabledi2c@ff650000rockchip,rk3288-i2ce <i2c;Ldefault(Hokayy2dpmic@1brockchip,rk808xin32kwifibt_32kin&1default (IJKL4+8LDLQ hregulatorsDCDC_REG1[vdd_armj~ q qh regulator-state-memDCDC_REG2[vdd_gpuj~ 5qhregulator-state-memDCDC_REG3 [vcc135_ddrj~regulator-state-memDCDC_REG4[vcc_18j~w@w@hregulator-state-memw@LDO_REG1 [vcc33_ioj~2Z2Zh4regulator-state-mem2ZLDO_REG3[vdd_10j~B@B@regulator-state-memB@LDO_REG7[vdd10_lcd_pwren_hj~&%&%regulator-state-memSWITCH_REG1 [vcc33_lcdj~hbregulator-state-memLDO_REG6 [vcc18_codecj~w@w@hcregulator-state-memLDO_REG4 [vccio_sdw@2Zhregulator-state-memLDO_REG5 [vcc33_sd2Z2Zhregulator-state-memLDO_REG8 [vcc33_ccdj~2Z2Zregulator-state-memLDO_REG2[mic_vccj~w@w@regulator-state-memi2c@ff660000rockchip,rk3288-i2cf =i2c;Ndefault(Mokayy2 max98090@10maxim,max98090&Nmclk;qdefault(Ohpwm@ff680000rockchip,rk3288-pwmh"default(P;_pwmokayhpwm@ff680010rockchip,rk3288-pwmh"default(Q;_pwmokayhpwm@ff680020rockchip,rk3288-pwmh "default(R;_pwm disabledpwm@ff680030rockchip,rk3288-pwmh0"default(S;_pwm disabledbus_intmem@ff700000 mmio-sramppsmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdshpower-controller!rockchip,rk3288-power-controller-uh hgpd_vio@9 ;chgfdehilkj$ATUVWXYZ[\pd_hevc@11 ;opA]^pd_video@12 ;A_pd_gpu@13 ;A`areboot-modesyscon-reboot-modeHORB[RBiRB yRBsyscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruvDHujk$#gׄeрxhрxhhsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfdwhDedp-phyrockchip,rk3288-dp-phy;h24mokayhwio-domains"rockchip,rk3288-io-voltage-domainokay444b c usbphyrockchip,rk3288-usb-phyokayusb-phy@320 ;]phyclk Zphy-resethGusb-phy@3344;^phyclk Zphy-resethEusb-phy@348H;_phyclk Zphy-resethFwatchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt;p Ookaysound@ff88b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif & hclkmclk;Tdtx 6default(eD disabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s & 5ddtxrxi2s_hclki2s_clk;Rdefault(f 7 Rokayhcypto-controller@ff8a0000rockchip,rk3288-crypto@ 0 ;}aclkhclksclkapb_pclk Zcrypto-rstokayiommu@ff900800rockchip,iommu@ iep_mmu; aclkiface l disablediommu@ff914000rockchip,iommu @P isp_mmu; aclkiface l y disabledrga@ff920000rockchip,rk3288-rga ;jaclkhclksclk g ilm Zcoreaxiahbvop@ff930000rockchip,rk3288-vop ;aclk_vopdclk_vophclk_vop g def Zaxiahbdclk hokayporth endpoint@0 ih~endpoint@1 jhyendpoint@2 khrendpoint@3 lhuiommu@ff930300rockchip,iommu  vopb_mmu; aclkiface g  lokayhhvop@ff940000rockchip,rk3288-vop ;aclk_vopdclk_vophclk_vop g  Zaxiahbdclk mokayporth endpoint@0 nhendpoint@1 ohzendpoint@2 phsendpoint@3 qhviommu@ff940300rockchip,iommu  vopl_mmu; aclkiface g  lokayhmmipi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi@ ;~d refpclk g D disabledportsportendpoint@0 rhkendpoint@1 shplvds@ff96c000rockchip,rk3288-lvds@;g pclk_lvdslcdc(t g D disabledportsport@0endpoint@0 uhlendpoint@1 vhqdp@ff970000rockchip,rk3288-dp@ b;icdppclkwdpoZdpDokaydefault(xportsport@0endpoint@0 yhjendpoint@1 zhoport@1endpoint@0 {hhdmi@ff980000rockchip,rk3288-dw-hdmi &D g;hmniahbisfrcec g okaydefaultunwedge(|Z}portsportendpoint@0 ~hiendpoint@1 hnvideo-codec@ff9a0000rockchip,rk3288-vpu   vepuvdpu; aclkhclk  g iommu@ff9a0800rockchip,iommu vpu_mmu; aclkiface l g hiommu@ff9c0440rockchip,iommu @@@ o hevc_mmu; aclkiface l disabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760$ jobmmugpu;  g okay hAgpu-opp-tableoperating-points-v2hopp-100000000{~opp-200000000{ ~opp-300000000{B@opp-400000000{ׄopp-600000000{#Fqos@ffaa0000syscon h`qos@ffaa0080syscon haqos@ffad0000syscon hUqos@ffad0100syscon hVqos@ffad0180syscon hWqos@ffad0400syscon hXqos@ffad0480syscon hYqos@ffad0500syscon hTqos@ffad0800syscon hZqos@ffad0880syscon h[qos@ffad0900syscon h\qos@ffae0000syscon h_qos@ffaf0000syscon h]qos@ffaf0080syscon h^efuse@ffb40000rockchip,rk3288-efuse ;q pclk_efusecpu_leakage@17interrupt-controller@ffc01000 arm,gic-400  @ @ `   hpinctrlrockchip,rk3288-pinctrlDdefaultsleep(Zgpio0@ff750000rockchip,gpio-banku Q;@     PMIC_SLEEP_APDDRIO_PWROFFDDRIO_RETENTS3A227E_INT_LPMIC_INT_LPWR_KEY_LAP_LID_INT_LEC_IN_RWAC_PRESENT_APRECOVERY_SW_LOTP_OUTHOST1_PWR_ENUSBOTG_PWREN_HAP_WARM_RESET_HnFALUT2I2C0_SDA_PMICI2C0_SCL_PMICSUSPEND_LUSB_INTh1gpio1@ff780000rockchip,gpio-bankx R;A    gpio2@ff790000rockchip,gpio-banky S;B    M CONFIG0CONFIG1CONFIG2CONFIG3EMMC_RST_LBL_PWR_ENAVDD_1V8_DISP_ENhgpio3@ff7a0000rockchip,gpio-bankz T;C     FLASH0_D0FLASH0_D1FLASH0_D2FLASH0_D3FLASH0_D4FLASH0_D5FLASH0_D6FLASH0_D7FLASH0_CS2/EMMC_CMDFLASH0_DQS/EMMC_CLKOgpio4@ff7b0000rockchip,gpio-bank{ U;D     UART0_RXDUART0_TXDUART0_CTSUART0_RTSSDIO0_D0SDIO0_D1SDIO0_D2SDIO0_D3SDIO0_CMDSDIO0_CLKBT_DEV_WAKEWIFI_ENABLE_HBT_ENABLE_LWIFI_HOST_WAKEBT_HOST_WAKEhgpio5@ff7c0000rockchip,gpio-bank| V;E    A SPI0_CLKSPI0_CS0SPI0_TXDSPI0_RXDVCC50_HDMI_ENhgpio6@ff7d0000rockchip,gpio-bank} W;F     I2S0_SCLKI2S0_LRCK_RXI2S0_LRCK_TXI2S0_SDII2S0_SDO0HP_DET_HALS_INTINT_CODECI2S0_CLKI2C2_SDAI2C2_SCLMICDETSDMMC_D0SDMMC_D1SDMMC_D2SDMMC_D3SDMMC_CLKSDMMC_CMDhNgpio7@ff7e0000rockchip,gpio-bank~ X;G     LCDC_BLPWM_LOGBL_ENTRACKPAD_INTTPM_INT_HSDMMC_DET_LAP_FLASH_WP_LEC_INTCPU_NMIDVSOKSDMMC_WPEDP_HPDDVS1nFALUT1LCD_ENDVS2VCC5V_GOOD_HI2C4_SDA_TPI2C4_SCL_TPI2C5_SDA_HDMII2C5_SCL_HDMI5V_DRVUART2_RXDUART2_TXDh gpio8@ff7f0000rockchip,gpio-bank Y;H    ^ RAM_ID0RAM_ID1RAM_ID2RAM_ID3I2C1_SDA_TPMI2C1_SCL_TPMSPI2_CLKSPI2_CS0SPI2_RXDSPI2_TXDhdmihdmi-cec-c0 hdmi-cec-c7 hdmi-ddc h|hdmi-ddc-unwedge h}vcc50-hdmi-en hpcfg-output-low %hpcfg-pull-up 0hpcfg-pull-down =hpcfg-pull-none Lhpcfg-pull-none-12ma L Y hsleepglobal-pwroff hddrio-pwroff hddr0-retention hddr1-retention edpedp-hpd  hxi2c0i2c0-xfer hHi2c1i2c1-xfer h.i2c2i2c2-xfer   hMi2c3i2c3-xfer h/i2c4i2c4-xfer h0i2c5i2c5-xfer h5i2s0i2s0-bus` hflcdclcdc-ctl@ htsdmmcsdmmc-clk hsdmmc-cmd hsdmmc-cd sdmmc-bus1 sdmmc-bus4@ hsdmmc-cd-disabled hsdmmc-cd-gpio hsdmmc-wp-gpio  hsdio0sdio0-bus1 sdio0-bus4@ hsdio0-cmd hsdio0-clk hsdio0-cd sdio0-wp sdio0-pwr sdio0-bkpwr sdio0-int wifienable-h hbt-enable-l hbt-host-wake hbt-dev-wake-sleep hbt-dev-wake-awake hsdio1sdio1-bus1 sdio1-bus4@ sdio1-cd sdio1-wp sdio1-bkpwr sdio1-int sdio1-cmd sdio1-clk sdio1-pwr  emmcemmc-clk hemmc-cmd hemmc-pwr  emmc-bus1 emmc-bus4@ emmc-bus8 hemmc-reset  hspi0spi0-clk  h!spi0-cs0  h$spi0-tx h"spi0-rx h#spi0-cs1 spi1spi1-clk  h&spi1-cs0  h)spi1-rx h(spi1-tx h'spi2spi2-cs1 spi2-clk h*spi2-cs0 h-spi2-rx h,spi2-tx  h+uart0uart0-xfer h6uart0-cts h7uart0-rts h8uart1uart1-xfer  h9uart1-cts  uart1-rts  uart2uart2-xfer h:uart3uart3-xfer h;uart3-cts  uart3-rts  uart4uart4-xfer h<uart4-cts  uart4-rts  tsadcotp-gpio  hBotp-out  hCpwm0pwm0-pin hPpwm1pwm1-pin hQpwm2pwm2-pin hRpwm3pwm3-pin hSgmacrgmii-pins  rmii-pins spdifspdif-tx  hepcfg-pull-none-drv-8ma L Yhpcfg-pull-up-drv-8ma 0 Ypcfg-output-high hhbuttonspwr-key-l hap-lid-int-l hpmicpmic-int-l hIdvs-1  hJdvs-2 hKrebootap-warm-reset-h  hrecovery-switchrec-mode-l  tpmtpm-int-h write-protectfw-wp-ap codechp-det hint-codec hOmic-det  hheadsetts3a227e-int-l h2backlightbl-en hbl_pwr_en  hchargerac-present-ap hcros-ecec-int h%suspendsuspend-l-wake hsuspend-l-sleep htrackpadtrackpad-int h3usb-hosthost1-pwr-en  husbotg-pwren-h  hbuck-5vdrv-5v hlcdlcd-en havdd-1v8-disp-en  hchosen tserial2:115200n8memorymemorybt-activity gpio-keysdefault(bt-wake BT Wakeup  power-button gpio-keysdefault(power Power 1 t dgpio-restart gpio-restart 1 default( emmc-pwrseqmmc-pwrseq-emmc(default hsdio-pwrseqmmc-pwrseq-simple; ext_clockdefault( hvcc-5vregulator-fixed[vcc_5vj~LK@LK@   default(hLvcc33-sysregulator-fixed [vcc33_sysj~2Z2Z hvcc50-hdmiregulator-fixed [vcc50_hdmij~ L  default(vdd-logicpwm-regulator [vdd_logic   { j~~psound!rockchip,rockchip-audio-max98090default( VEYRON-I2S ! 9 NN dN  {backlightpwm-backlight   !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~  default( B@   hgpio-charger gpio-charger mains 1default(lid-switch gpio-keysdefault(lid Lid 1   panelinnolux,n116bgesimple-panelokay  portsportendpoint h{vccsysregulator-fixed[vccsys~jhvcc5-host1-regulatorregulator-fixed  1 default( [vcc5_host1j~vcc5v-otg-regulatorregulator-fixed  1 default( [vcc5_host2j~panel-regulatorregulator-fixed  default([panel_regulator % hvcc18-lcdregulator-fixed  default( [vcc18_lcdj~ backlight-regulatorregulator-fixed  default([backlight_regulator  %:h #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2i2c20interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksdynamic-power-coefficientcpu0-supplyphandleopp-sharedopp-hzopp-microvoltranges#dma-cellsarm,pl330-broken-no-flushpclock-namesstatusclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendportsmax-frequencyfifo-depthreset-namesbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaycd-gpiosrockchip,default-sample-phasesd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplypinctrl-namespinctrl-0wp-gpioscap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removabledisable-wpmmc-hs200-1_8v#io-channel-cellsdmasdma-namesgoogle,cros-ec-spi-pre-delayspi-max-frequencygoogle,remote-bussbs,i2c-retry-countsbs,poll-retry-countkeypad,num-rowskeypad,num-columnsgoogle,needs-ghost-filterlinux,keymaprx-sample-delay-nsi2c-scl-falling-time-nsi2c-scl-rising-time-nspowered-while-suspendedti,micbiasvcc-supplywakeup-sourcereg-shiftreg-io-widthpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesphysphy-namesneeds-reset-on-resumedr_modesnps,reset-phy-on-wakesnps,need-phy-for-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeassigned-clocksassigned-clock-parentsrockchip,system-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc12-supplyvddio-supplyvcc10-supplyvcc9-supplyvcc11-supplydvs-gpiosregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvolt#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsbb-supplydvp-supplyflash0-supplygpio1830-supplygpio30-supplylcdc-supplywifi-supplyaudio-supplysdcard-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointmali-supplyinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsgpio-line-namesrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highstdout-pathlabellinux,codedebounce-intervalpriorityreset-gpiosvin-supplyenable-active-highgpiopwmspwm-supplypwm-dutycycle-rangepwm-dutycycle-unitrockchip,modelrockchip,i2s-controllerrockchip,audio-codecrockchip,hp-det-gpiosrockchip,mic-det-gpiosrockchip,headset-codecbrightness-levelsdefault-brightness-levelenable-gpiospost-pwm-on-delay-mspwm-off-delay-mspower-supplycharger-typelinux,input-typebacklightstartup-delay-us