581(1)STMicroelectronics STM32H743i-EVAL board !st,stm32h743i-evalst,stm32h743interrupt-controller@e000e100!arm,armv7m-nvic,AR Vtimer@e000e010!arm,armv7m-systickR^okaye沀soc !simple-busutimer@40000c00!st,stm32-timerR@ 2_timer@40002400!st,stm32-lptimerR@$mux ^disabledpwm!st,stm32-pwm-lp ^disabledtrigger@0!st,stm32-lptimer-triggerR ^disabledcounter!st,stm32-lptimer-counter ^disabledspi@40003800!st,stm32h7-spiR@8$ ^disabledspi@40003c00!st,stm32h7-spiR@<3 ^disabledserial@40004400!st,stm32f7-uartR@D& ^disabledi2c@40005400!st,stm32f7-i2cR@T ^okaydefaulti2c@40005800!st,stm32f7-i2cR@X!" ^disabledi2c@40005C00!st,stm32f7-i2cR@\HI ^disableddac@40007400!st,stm32h7-dac-coreR@tXpclk ^disableddac@1 !st,stm32-dacR ^disableddac@2 !st,stm32-dacR ^disabledserial@40011000!st,stm32f7-uartR@%^okaydefaultspi@40013000!st,stm32h7-spiR@0# ^disabledspi@40013400!st,stm32h7-spiR@4T ^disabledspi@40015000!st,stm32h7-spiR@PU ^disableddma@40020000 !st,stm32-dmaR@ /A"- ^disabledVdma@40020400 !st,stm32-dmaR@ 89:;<DEF@"- ^disabledVdma-router@40020800!st,stm32h7-dmamuxR@:-GAadc@40022000!st,stm32h7-adc-coreR@ }bus,A^okaySVadc@0!st,stm32h7-adc_Ru^okayqadc@100!st,stm32h7-adc_Ru ^disabledusb@40040000!st,stm32f7-hsotgR@M|otg  @@@@ ^okay default  usb2-phyotgusb@40080000!st,stm32f4x9-fsotgR@e{otg ^disableddma@52000000!st,stm32h7-mdmaRRz9:- sdmmc@52007000!arm,pl18xarm,primecell1RRp1cmd_irqx apb_pclk'defaultopendrainsleep  *4>IUak^okayinterrupt-controller@58000000!st,stm32h7-exti,ARX4 ()>LVsystem-config@58000400!sysconRXVspi@58001400!st,stm32h7-spiRXV ^disabledi2c@58001C00!st,stm32f7-i2cRX_` ^disabledtimer@58002400!st,stm32-lptimerRX$mux ^disabledpwm!st,stm32-pwm-lp ^disabledtrigger@1!st,stm32-lptimer-triggerR ^disabledcounter!st,stm32-lptimer-counter ^disabledtimer@58002800!st,stm32-lptimerRX(mux ^disabledpwm!st,stm32-pwm-lp ^disabledtrigger@2!st,stm32-lptimer-triggerR ^disabledtimer@58002c00!st,stm32-lptimerRX,mux ^disabledpwm!st,stm32-pwm-lp ^disabledtimer@58003000!st,stm32-lptimerRX0mux ^disabledpwm!st,stm32-pwm-lp ^disabledregulator@58003c00!st,stm32-vrefbufRX<mw`&% ^disabledrtc@58004000!st,stm32h7-rtcRX@l  pclkrtc_ck  ualarm ^okayreset-clock-controller@58024400!st,stm32h743-rccst,stm32-rccRXD Vpower-config@58024800!sysconRXHVadc@58026000!st,stm32h7-adc-coreRX`bus,A ^disabledVadc@0!st,stm32h7-adc_Ru ^disabledethernet@40028000 !st,stm32-dwmacsnps,dwmac-4.10aR@ stmmaceth=macirq stmmacethmac-clk-txmac-clk-rx>=< ^disableddefaultrmiimdio0!snps,dwmac-mdioethernet-phy@0RVpin-controller!st,stm32h743-pinctrl X0u#gpio@580200005ERVQGPIOA,Agpio@580204005ERUQGPIOB,Agpio@580208005ERTQGPIOC,Agpio@58020c005ER SQGPIOD,Agpio@580210005ERRQGPIOE,Agpio@580214005ERQQGPIOF,Agpio@580218005ERPQGPIOG,Agpio@58021c005EROQGPIOH,Agpio@580220005ER NQGPIOI,Agpio@580224005ER$MQGPIOJ,Agpio@580228005ER(LQGPIOK,Ai2c1@0Vpins^errmii@0Vpins$^k m l $ %  !   sdmmc1-b4-0V pins^( ) * + , 2 esdmmc1-b4-od-0V pins1^( ) * + , epins2^2 resdmmc1-b4-sleep-0Vpins^()*+,2sdmmc1-dir-0V pins1 ^& ' pins2^sdmmc1-dir-sleep-0Vpins^&'usart1@0Vpins1^epins2^eusart2@0pins1^5epins2^6eusbotg-hs@0V pins0^t          eclocksclk-hse !fixed-clocke}x@Vclk-lse !fixed-clockeVi2s_ckin !fixed-clockeVchosenroot=/dev/ramserial0:115200n8memorymemoryRaliases/soc/serial@40011000regulator-vdda!regulator-fixedvddaw2Z2ZVregulator-v2v9_sd!regulator-fixedv2v9_sdw,@ ,@ Vusb-phy!usb-nop-xceiv; main_clkV  #address-cells#size-cellsmodelcompatibleinterrupt-controller#interrupt-cellsregphandlestatusclock-frequencyinterrupt-parentrangesinterruptsclocksclock-names#pwm-cellsresetspinctrl-0pinctrl-namesi2c-scl-rising-time-nsi2c-scl-falling-time-ns#io-channels-cells#dma-cellsst,mem2memdma-requestsdma-channelsdma-mastersvref-supply#io-channel-cellsst,adc-channelsg-rx-fifo-sizeg-np-tx-fifo-sizeg-tx-fifo-sizephysphy-namesdr_modearm,primecell-periphidinterrupt-namescap-sd-highspeedcap-mmc-highspeedmax-frequencypinctrl-1pinctrl-2broken-cdst,sig-dirst,neg-edgest,use-ckinbus-widthvmmc-supplyregulator-min-microvoltregulator-max-microvoltassigned-clocksassigned-clock-parentsst,syscfg#clock-cells#reset-cellsreg-namesst,sysconsnps,pblphy-modephy-handlepins-are-numberedgpio-controller#gpio-cellsst,bank-namepinmuxbias-disabledrive-open-drainslew-ratedrive-push-pullbias-pull-upbootargsstdout-pathdevice_typeserial0regulator-nameregulator-always-on#phy-cells