T8(T~tcl,am335x-sl50ti,am33xx +7Toby Churchill SL50 Serieschosen=/ocp/serial@44e09000aliasesI/ocp/i2c@44e0b000N/ocp/i2c@4802a000S/ocp/i2c@4819c000X/ocp/serial@44e09000`/ocp/serial@48022000h/ocp/serial@48024000p/ocp/serial@481a6000x/ocp/serial@481a8000/ocp/serial@481aa000/ocp/can@481cc000/ocp/can@481d0000/ocp/usb@47400000/usb@47401000/ocp/usb@47400000/usb@47401800#/ocp/usb@47400000/usb-phy@47401300#/ocp/usb@47400000/usb-phy@47401b00&/ocp/ethernet@4a100000/slave@4a100200&/ocp/ethernet@4a100000/slave@4a100300/ocp/spi@48030000/ocp/spi@481a0000cpus+cpu@0arm,cortex-a8cpucpu opp-tableoperating-points-v2-ti-cpu opp50-300000000( /~4(=Nopp100-275000000(d* /r=Nopp100-300000000( /r= Nopp100-500000000(e /r=opp100-600000000(#F /r=@opp120-600000000(#F /O@=opp120-720000000(*T /O@=oppturbo-720000000(*T /9pP=oppturbo-800000000(/ /9pP=oppnitro-1000000000(; /7DL=pmu@4b000000arm,cortex-a8-pmuZKedebugsssocti,omap-inframpu ti,omap3-mpuempuocp simple-bus+oel3_mainl4_wkup@44c00000ti,am3-l4-wkupsimple-bus+ oD(wkup_m3@100000ti,am3352-wkup-m3@  vumemdmemewkup_m3am335x-pm-firmware.elf "prcm@200000ti,am3-prcmsimple-bus @+ o @clocks+clk_32768_ck fixed-clock clk_rc32k_ck fixed-clock} virt_19200000_ck fixed-clock$ virt_24000000_ck fixed-clockn6 virt_25000000_ck fixed-clock}x@ virt_26000000_ck fixed-clock tclkin_ck fixed-clock dpll_core_ck@490ti,am3-dpll-core-clock \h dpll_core_x2_ckti,am3-dpll-x2-clock dpll_core_m4_ck@480ti,divider-clock dpll_core_m5_ck@484ti,divider-clock dpll_core_m6_ck@4d8ti,divider-clockdpll_mpu_ck@488ti,am3-dpll-clock  , dpll_mpu_m2_ck@4a8ti,divider-clockdpll_ddr_ck@494ti,am3-dpll-no-gate-clock 4@ dpll_ddr_m2_ck@4a0ti,divider-clock  dpll_ddr_m2_div2_ckfixed-factor-clock dpll_disp_ck@498ti,am3-dpll-no-gate-clock HT dpll_disp_m2_ck@4a4ti,divider-clock  dpll_per_ck@48c!ti,am3-dpll-no-gate-j-type-clock p dpll_per_m2_ck@4acti,divider-clock  dpll_per_m2_div4_wkupdm_ckfixed-factor-clock dpll_per_m2_div4_ckfixed-factor-clock clk_24mhzfixed-factor-clock  clkdiv32k_ckfixed-factor-clockl3_gclkfixed-factor-clock pruss_ocp_gclk@530 ti,mux-clock0mmu_fck@914ti,gate-clock timer1_fck@528 ti,mux-clock8( 8timer2_fck@508 ti,mux-clock8 9timer3_fck@50c ti,mux-clock8 timer4_fck@510 ti,mux-clock8timer5_fck@518 ti,mux-clock8timer6_fck@51c ti,mux-clock8timer7_fck@504 ti,mux-clock8usbotg_fck@47cti,gate-clock |dpll_core_m4_div2_ckfixed-factor-clock ieee5000_fck@e4ti,gate-clockwdt1_fck@538 ti,mux-clock88l4_rtc_gclkfixed-factor-clockl4hs_gclkfixed-factor-clockl3s_gclkfixed-factor-clockl4fw_gclkfixed-factor-clockl4ls_gclkfixed-factor-clock !sysclk_div_ckfixed-factor-clockcpsw_125mhz_gclkfixed-factor-clock Ccpsw_cpts_rft_clk@520 ti,mux-clock  Dgpio0_dbclk_mux_ck@53c ti,mux-clock8<lcd_gclk@534 ti,mux-clock  4 mmc_clkfixed-factor-clock gfx_fclk_clksel_ck@52c ti,mux-clock , gfx_fck_div_ck@52cti,divider-clock,sysclkout_pre_ck@700 ti,mux-clock  clkout2_div_ck@700ti,divider-clock clkout2_ck@700ti,gate-clockclockdomainsl4_per_cm@0 ti,omap4-cm+ oclk@14 ti,clkctrl< l4_wkup_cm@400 ti,omap4-cm+ oclk@4 ti,clkctrlmpu_cm@600 ti,omap4-cm+ oclk@4 ti,clkctrll4_rtc_cm@800 ti,omap4-cm+ oclk@0 ti,clkctrlgfx_l3_cm@900 ti,omap4-cm + o clk@4 ti,clkctrll4_cefuse_cm@a00 ti,omap4-cm + o clk@20 ti,clkctrl scm@210000ti,am3-scmsimple-bus! + o! pinmux@800pinctrl-single8+ 0Mdefault[pinmux_led_pins eTX\` Kpinmux_uart0_pinsep0t )pinmux_uart1_pinse0 *pinmux_uart4_pinsep6t +pinmux_i2c0_pinse00 ,pinmux_i2c2_pinsex3|3 -cpsw_defaulthe00 $(,0004080<0@0 Ecpsw_sleephe'''' '$'(','0'4'8'<'@' Fdavinci_mdio_defaulteH0L Gdavinci_mdio_sleepeH'L' Hpinmux_mmc1_pinsel/ 1pinmux_emmc_pwrseq_pinseP Ppinmux_emmc_pinsPe22111 11111 4pinmux_audio_pins(e     Jpinmux_ehrpwm1a_pinseHL Apinmux_spi0_pins(eT0X0P0\0`0 :pinmux_lwb_pins@e(074787D7@7<7 scm_conf@0sysconsimple-bus+ o clocks+sys_clkin_ck@40 ti,mux-clock @ adc_tsc_fckfixed-factor-clockdcan0_fckfixed-factor-clock 6dcan1_fckfixed-factor-clock 7mcasp0_fckfixed-factor-clockmcasp1_fckfixed-factor-clocksmartreflex0_fckfixed-factor-clocksmartreflex1_fckfixed-factor-clocksha0_fckfixed-factor-clockaes0_fckfixed-factor-clockrng_fckfixed-factor-clockehrpwm0_tbclk@44e10664ti,gate-clock!d ?ehrpwm1_tbclk@44e10664ti,gate-clock!d @ehrpwm2_tbclk@44e10664ti,gate-clock!d Bwkup_m3_ipc@1324ti,am3352-wkup-m3-ipc$$ZNy"#$dma-router@f90ti,am335x-edma-crossbar@ % 0clockdomainsinterrupt-controller@48200000ti,am33xx-intcH  edma@49000000ti,edma3-tpccetpccI vedma3_cc Z 'edma3_ccintedma3_mperredma3_ccerrint@&'( %tptc@49800000ti,edma3-tptcetptc0IZpedma3_tcerrint &tptc@49900000ti,edma3-tptcetptc1IZqedma3_tcerrint 'tptc@49a00000ti,edma3-tptcetptc2IZredma3_tcerrint (gpio@44e07000ti,omap4-gpioegpio1DpZ`gpio@4804c000ti,omap4-gpioegpio2HZb 2gpio@481ac000ti,omap4-gpioegpio3HZ gpio@481ae000ti,omap4-gpioegpio4HZ>serial@44e09000ti,am3352-uartti,omap3-uarteuart1lD ZH okay'%%,txrxMdefault[)serial@48022000ti,am3352-uartti,omap3-uarteuart2lH ZI okay'%%,txrxMdefault[*serial@48024000ti,am3352-uartti,omap3-uarteuart3lH@ ZJ  disabled'%%,txrxserial@481a6000ti,am3352-uartti,omap3-uarteuart4lH` Z,  disabledserial@481a8000ti,am3352-uartti,omap3-uarteuart5lH Z- okayMdefault[+serial@481aa000ti,am3352-uartti,omap3-uarteuart6lH Z.  disabledi2c@44e0b000 ti,omap4-i2c+ei2c1DZF okayMdefault[,tps@24$ ti,tps652176 Zchargerti,tps65217-chargerZUSBAC  disabledpwrbuttonti,tps65217-pwrbuttonZ  disabledregulators+regulator@0Rdcdc1g``regulator@1Rdcdc2vdd_mpugH7 regulator@2Rdcdc3 vdd_coregH0regulator@3Rldo1gw@w@regulator@4Rldo2g2Z2Zregulator@5Rldo3gw@w@ /regulator@6Rldo4g2Z2Z .rtc@68 ti,bq32000`heeprom@50 atmel,24c256Pmcp23017@20microchip,mcp23017 i2c@4802a000 ti,omap4-i2c+ei2c2HZG  disabledi2c@4819c000 ti,omap4-i2c+ei2c3HZ okayMdefault[-tlv320aic3106@1b okayti,tlv320aic3106.../ Misl29023@44isil,isl29023Dmmc@48060000ti,omap4-hsmmcemmc1!8 '00,txrxZ@H okayMdefault[1U _2 h3mmc@481d8000ti,omap4-hsmmcemmc2!'%%,txrxZH okayMdefault[4Uh3t5mmc@47810000ti,omap4-hsmmcemmc3!ZG  disabledspinlock@480ca000ti,omap4-hwspinlockH  espinlockwdt@44e35000 ti,omap3-wdt ewd_timer2DPZ[can@481cc000ti,am3352-d_caned_can0H 6fck DZ4  disabledcan@481d0000ti,am3352-d_caned_can1H 7fck DZ7  disabledmailbox@480c8000ti,omap4-mailboxH ZMemailbox #wkup_m3   $timer@44e31000ti,am335x-timer-1msDZCetimer18fcktimer@48040000ti,am335x-timerHZDetimer29fcktimer@48042000ti,am335x-timerH ZEetimer3timer@48044000ti,am335x-timerH@Z\etimer4timer@48046000ti,am335x-timerH`Z]etimer5timer@48048000ti,am335x-timerHZ^etimer6timer@4804a000ti,am335x-timerHZ_etimer7rtc@44e3e000ti,am3352-rtcti,da830-rtcDZKLertc 8int-clk  disabledspi@48030000ti,omap4-mcspi+HZAespi00'%%%%,tx0rx0tx1rx1 okayMdefault[:n25q032@1+micron,n25q032LK@spi@481a0000ti,omap4-mcspi+HZ}espi10'%*%+%,%-,tx0rx0tx1rx1  disabledusb@47400000ti,am33xx-usbG@o+ eusb_otg_hs okaycontrol@44e10620ti,am335x-usb-ctrl-moduleD DHvphy_ctrlwakeup okay ;usb-phy@47401300ti,am335x-usb-phyG@vphy okay1;= <usb@47401000ti,musb-am33xx okayG@G@ vmccontrolZmc HperipheralPbq <h'========== = = = = =========== = = = = =,rx1rx2rx3rx4rx5rx6rx7rx8rx9rx10rx11rx12rx13rx14rx15tx1tx2tx3tx4tx5tx6tx7tx8tx9tx10tx11tx12tx13tx14tx15usb-phy@47401b00ti,am335x-usb-phyG@vphy okay1;= >usb@47401800ti,musb-am33xx okayG@G@ vmccontrolZmcHhostPbq >h'==============================,rx1rx2rx3rx4rx5rx6rx7rx8rx9rx10rx11rx12rx13rx14rx15tx1tx2tx3tx4tx5tx6tx7tx8tx9tx10tx11tx12tx13tx14tx15dma-controller@47402000ti,am3359-cppi41 G@G@ G@0G@@@#vgluecontrollerschedulerqueuemgrZglue okay =epwmss@48300000ti,am33xx-pwmssH0eepwmss0+  disabled$oH0H0H0H0H0H0ecap@48300100ti,am3352-ecapti,am33xx-ecapH0!fckZecap0  disabledpwm@48300200"ti,am3352-ehrpwmti,am33xx-ehrpwmH0?! tbclkfck  disabledepwmss@48302000ti,am33xx-pwmssH0 eepwmss1+ okay$oH0!H0!H0!H0!H0"H0"ecap@48302100ti,am3352-ecapti,am33xx-ecapH0!!fckZ/ecap1  disabledpwm@48302200"ti,am3352-ehrpwmti,am33xx-ehrpwmH0"@! tbclkfck okayMdefault[A Lepwmss@48304000ti,am33xx-pwmssH0@eepwmss2+  disabled$oH0AH0AH0AH0AH0BH0Becap@48304100ti,am3352-ecapti,am33xx-ecapH0A!fckZ=ecap2  disabledpwm@48304200"ti,am3352-ehrpwmti,am33xx-ehrpwmH0BB! tbclkfck  disabledethernet@4a100000ti,am335x-cpswti,cpswecpgmac0CD fckcpts  JJ+Z()*+o okayMdefaultsleep[E"Fmdio@4a101000ti,cpsw-mdioti,davinci_mdio+ edavinci_mdio,B@J okayMdefaultsleep[G"H Islave@4a1002005AIHmiislave@4a1003005AIHmiicpsw-phy-sel@44e10650ti,am3352-cpsw-phy-selDP vgmii-selocmcram@40300000 mmio-sram@0elm@48080000ti,am3352-elmH Zeelm  disabledlcdc@4830e000ti,am33xx-tilcdcH0Z$elcdc  disabledtscadc@44e0d000ti,am3359-tscadcDZeadc_tsc  disabled'%5%9 ,fifo0fifo1tscti,am3359-tscadcQti,am3359-adcemif@4c000000ti,emif-am3352Leemifgpmc@50000000ti,am3352-gpmcegpmccP Zd '%4,rxtxv+  disabledsham@53100000ti,omap4-shameshamSZm '%$,rx okayaes@53500000 ti,omap4-aeseaesSPZg'%%,txrx okaymcasp@48038000ti,am33xx-mcasp-audioemcasp0H F@vmpudatZPQtxrx okay'%% ,txrxMdefault[J@ Nmcasp@4803c000ti,am33xx-mcasp-audioemcasp1H F@@vmpudatZRStxrx  disabled'% % ,txrxrng@48310000 ti,omap4-rngerngH1 Zomemory@80000000memoryԀ leds gpio-ledsMdefault[Kled0sl50:green:usr0 b2offled1sl50:red:usr1 b2offled2sl50:green:usr2 b2offled3sl50:red:usr3 b2offdisp0pwm-backlightL , (2<FPZcdisp1pwm-backlightL , (2<FPZcclocks simple-bus+oscillator@0 fixed-clockw Osoundti,da830-evm-audio  AM335x-SL50M#NOmclkJ7Headphone JackHPLOUTHeadphone JackHPROUTLINE1RLine InLINE1LLine Inpwrseq@0mmc-pwrseq-emmcMdefault[P H2 5fixedregulator0regulator-fixed vmmcsd_fixedg2Z2Z 3 compatibleinterrupt-parent#address-cells#size-cellsmodelstdout-pathi2c0i2c1i2c2serial0serial1serial2serial3serial4serial5d_can0d_can1usb0usb1phy0phy1ethernet0ethernet1spi0spi1device_typeregoperating-points-v2clocksclock-namesclock-latencycpu0-supplysysconphandleopp-hzopp-microvoltopp-supported-hwopp-suspendinterruptsti,hwmodsrangesreg-namesti,pm-firmware#clock-cellsclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-rate-parentti,bit-shift#pinctrl-cellspinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinsti,rprocmboxes#dma-cellsdma-requestsdma-mastersinterrupt-controller#interrupt-cellsinterrupt-namesti,tptcsti,edma-memcpy-channelsgpio-controller#gpio-cellsstatusdmasdma-namesti,pmic-shutdown-controllerregulator-compatibleregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-nameregulator-boot-ontrickle-resistor-ohmsAVDD-supplyIOVDD-supplyDRVDD-supplyDVDD-supplyti,dual-voltti,needs-special-resetti,needs-special-hs-handlingbus-widthcd-gpiosvmmc-supplymmc-pwrseq#hwlock-cellssyscon-raminit#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-send-noirqti,mbox-txti,mbox-rxti,timer-alwonti,timer-pwmti,spi-num-csspi-max-frequencyti,ctrl_mod#phy-cellsdr_modementor,multipointmentor,num-epsmentor,ram-bitsmentor,powerphys#dma-channels#dma-requests#pwm-cellscpdma_channelsale_entriesbd_ram_sizemac_controlslavesactive_slavecpts_clock_multcpts_clock_shiftpinctrl-1bus_freqmac-addressphy_idphy-mode#io-channel-cellsti,no-idle-on-initgpmc,num-csgpmc,num-waitpinsop-modetdm-slotsserial-dirtx-num-evtrx-num-evtlabeldefault-statepwmsbrightness-levelsdefault-brightness-levelti,modelti,audio-codecti,mcasp-controllerti,audio-routingreset-gpios