J8( bа%motorola,droid4ti,omap4430ti,omap4 +7Motorola Droid 4 XT894chosen=/ocp/serial@48020000aliasesI/ocp/i2c@48070000N/ocp/i2c@48072000S/ocp/i2c@48060000X/ocp/i2c@48350000]/ocp/serial@4806a000e/ocp/serial@4806c000m/ocp/serial@48020000u/ocp/serial@4806e000+}/ocp/dss@58000000/encoder@58004000/display /connectorcpus+cpu@0arm,cortex-a9cpucpu  'O 5acpu@1arm,cortex-a9cpupmuarm,cortex-a9-pmudebugssinterrupt-controller@48241000arm,cortex-a9-gic'<H$H$ l2-cache-controller@48242000arm,pl310-cacheH$ M[local-timer@48240600arm,cortex-a9-twd-timerH$  g  interrupt-controller@48281000ti,omap4-wugen-mpu'<H( socti,omap-inframpu ti,omap4-mpumpurdsp ti,omap3-c64dspiva ti,ivahdivaocpti,omap4-l3-nocsimple-bus+wl3_main_1l3_main_2l3_main_3DD Eg  l4@4a000000ti,omap4-l4-cfgsimple-bus+ wJcm1@4000ti,omap4-cm1simple-bus@ + w@ clocks+extalt_clkin_ck~ fixed-clockDpad_clks_src_ck~ fixed-clockpad_clks_ck@108~ti,gate-clockpad_slimbus_core_clks_ck~ fixed-clocksecure_32k_clk_src_ck~ fixed-clockslimbus_src_clk~ fixed-clockslimbus_clk@108~ti,gate-clock sys_32k_ck~ fixed-clock0virt_12000000_ck~ fixed-clock2virt_13000000_ck~ fixed-clock]@3virt_16800000_ck~ fixed-clockY4virt_19200000_ck~ fixed-clock$5virt_26000000_ck~ fixed-clock6virt_27000000_ck~ fixed-clock7virt_38400000_ck~ fixed-clockI8tie_low_clock_ck~ fixed-clockutmi_phy_clkout_ck~ fixed-clockxclk60mhsp1_ck~ fixed-clockxclk60mhsp2_ck~ fixed-clockxclk60motg_ck~ fixed-clockdpll_abe_ck@1e0~ti,omap4-dpll-m4xen-clock  dpll_abe_x2_ck@1f0~ti,omap4-dpll-x2-clock  dpll_abe_m2x2_ck@1f0~ti,divider-clock  abe_24m_fclk~fixed-factor-clock abe_clk@108~ti,divider-clock dpll_abe_m3x2_ck@1f4~ti,divider-clock core_hsd_byp_clk_mux_ck@12c~ ti,mux-clock,dpll_core_ck@120~ti,omap4-dpll-core-clock $,(dpll_core_x2_ck~ti,omap4-dpll-x2-clockdpll_core_m6x2_ck@140~ti,divider-clock@dpll_core_m2_ck@130~ti,divider-clock0ddrphy_ck~fixed-factor-clockdpll_core_m5x2_ck@13c~ti,divider-clock<div_core_ck@100~ti,divider-clockdiv_iva_hs_clk@1dc~ti,divider-clockdiv_mpu_hs_clk@19c~ti,divider-clockdpll_core_m4x2_ck@138~ti,divider-clock8dll_clk_div_ck~fixed-factor-clockdpll_abe_m2_ck@1f0~ti,divider-clock "dpll_core_m3x2_gate_ck@134~ ti,composite-no-wait-gate-clock4dpll_core_m3x2_div_ck@134~ti,composite-divider-clock4dpll_core_m3x2_ck~ti,composite-clock=dpll_core_m7x2_ck@144~ti,divider-clockDiva_hsd_byp_clk_mux_ck@1ac~ ti,mux-clockdpll_iva_ck@1a0~ti,omap4-dpll-clock.7dpll_iva_x2_ck~ti,omap4-dpll-x2-clockdpll_iva_m4x2_ck@1b8~ti,divider-clock.~dpll_iva_m5x2_ck@1bc~ti,divider-clock.] dpll_mpu_ck@160~ti,omap4-dpll-clock`dlhdpll_mpu_m2_ck@170~ti,divider-clockpper_hs_clk_div_ck~fixed-factor-clock#usb_hs_clk_div_ck~fixed-factor-clock)l3_div_ck@100~ti,divider-clock l4_div_ck@100~ti,divider-clock lp_clk_div_ck~fixed-factor-clock 9mpu_periphclk~fixed-factor-clockocp_abe_iclk@528~ti,divider-clock !(Cper_abe_24m_fclk~fixed-factor-clock"dummy_ck~ fixed-clockclockdomainsmpuss_cm@300 ti,omap4-cm+ wclk@20 ti,clkctrl ~tesla_cm@400 ti,omap4-cm+ wclk@20 ti,clkctrl ~abe_cm@500 ti,omap4-cm+ wclk@20 ti,clkctrl l~!cm2@8000ti,omap4-cm2simple-bus0+ w0clocks+per_hsd_byp_clk_mux_ck@14c~ ti,mux-clock#L$dpll_per_ck@140~ti,omap4-dpll-clock$@DLH%dpll_per_m2_ck@150~ti,divider-clock%P-dpll_per_x2_ck@150~ti,omap4-dpll-x2-clock%P&dpll_per_m2x2_ck@150~ti,divider-clock&P,dpll_per_m3x2_gate_ck@154~ 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ti,clkctrl ~ducati_cm@900 ti,omap4-cm + w clk@20 ti,clkctrl ~l3_dma_cm@a00 ti,omap4-cm + w clk@20 ti,clkctrl ~l3_emif_cm@b00 ti,omap4-cm + w clk@20 ti,clkctrl ~d2d_cm@c00 ti,omap4-cm + w clk@20 ti,clkctrl ~l4_cfg_cm@d00 ti,omap4-cm + w clk@20 ti,clkctrl ~l3_instr_cm@e00 ti,omap4-cm+ wclk@20 ti,clkctrl $~ivahd_cm@f00 ti,omap4-cm+ wclk@20 ti,clkctrl ~iss_cm@1000 ti,omap4-cm+ wclk@20 ti,clkctrl ~zl3_dss_cm@1100 ti,omap4-cm+ wclk@20 ti,clkctrl ~l3_gfx_cm@1200 ti,omap4-cm+ wclk@20 ti,clkctrl ~l3_init_cm@1300 ti,omap4-cm+ wclk@20 ti,clkctrl ~yl4_per_cm@1400 ti,omap4-cm+ wclk@20 ti,clkctrl D~]scm@2000ti,omap4-scm-coresimple-bus + w ctrl_module_corescm_conf@0syscon+scm@100000%ti,omap4-scm-padconf-coresimple-bus+ wctrl_module_pad_corepinmux@40 ti,omap4-padconfpinctrl-single@+j<'y_pinmux_hdmi_hpd_pinsXpinmux_dss_hdmi_pinsZ\^pinmux_poweroff_pins4pinmux_tmp105_irqNcpinmux_usb_gpio_mux_sel1_pinsHmpinmux_touchscreen_pins`dpinmux_als_proximity_pinsLepinmux_usb_ulpi_pinspVXrtvxz|~opinmux_usb_utmi_pinspVXrtvxz|~ppinmux_uart3_pinspVXrtvxz|~qpinmux_uart4_pins `omap4_padconf_global@5a0sysconsimple-busp+ wp1pbias_regulator@60ti,pbias-omap4ti,pbias-omap`1pbias_mmc_omap4pbias_mmc_omap4w@-tl4@300000ti,omap4-l4-wkupsimple-bus+ w0counter@4000ti,omap-counter32k@  counter_32kprm@6000 ti,omap4-prm`0 g + w`0clocks+sys_clkin_ck@110~ ti,mux-clock2345678abe_dpll_bypass_clk_mux_ck@108~ ti,mux-clock0 abe_dpll_refclk_mux_ck@10c~ ti,mux-clock0  dbgclk_mux_ck~fixed-factor-clockl4_wkup_clk_mux_ck@108~ ti,mux-clock9syc_clk_div_ck@100~ti,divider-clockusim_ck@1858~ti,divider-clock.XC:usim_fclk@1858~ti,gate-clock:Xtrace_clk_div_ck~ti,clkdm-gate-clock ;<bandgap_fclk@1888~ti,gate-clock0clockdomainsemu_sys_clkdmti,clockdomain<l4_wkup_cm@1800 ti,omap4-cm+ wclk@20 ti,clkctrl \~}emu_sys_cm@1a00 ti,omap4-cm+ wclk@20 ti,clkctrl ~;scrm@a000ti,omap4-scrm clocks+auxclk0_src_gate_ck@310~ ti,composite-no-wait-gate-clock=?auxclk0_src_mux_ck@310~ti,composite-mux-clock =>@auxclk0_src_ck~ti,composite-clock?@Aauxclk0_ck@310~ti,divider-clockAQauxclk1_src_gate_ck@314~ ti,composite-no-wait-gate-clock=Bauxclk1_src_mux_ck@314~ti,composite-mux-clock =>Cauxclk1_src_ck~ti,composite-clockBCDauxclk1_ck@314~ti,divider-clockDRauxclk2_src_gate_ck@318~ ti,composite-no-wait-gate-clock=Eauxclk2_src_mux_ck@318~ti,composite-mux-clock =>Fauxclk2_src_ck~ti,composite-clockEFGauxclk2_ck@318~ti,divider-clockGSauxclk3_src_gate_ck@31c~ ti,composite-no-wait-gate-clock=Hauxclk3_src_mux_ck@31c~ti,composite-mux-clock =>Iauxclk3_src_ck~ti,composite-clockHIJauxclk3_ck@31c~ti,divider-clockJTauxclk4_src_gate_ck@320~ ti,composite-no-wait-gate-clock= Kauxclk4_src_mux_ck@320~ti,composite-mux-clock => Lauxclk4_src_ck~ti,composite-clockKLMauxclk4_ck@320~ti,divider-clockM Uauxclk5_src_gate_ck@324~ ti,composite-no-wait-gate-clock=$Nauxclk5_src_mux_ck@324~ti,composite-mux-clock =>$Oauxclk5_src_ck~ti,composite-clockNOPauxclk5_ck@324~ti,divider-clockP$Vauxclkreq0_ck@210~ ti,mux-clockQRSTUVauxclkreq1_ck@214~ ti,mux-clockQRSTUVauxclkreq2_ck@218~ ti,mux-clockQRSTUVauxclkreq3_ck@21c~ ti,mux-clockQRSTUVauxclkreq4_ck@220~ ti,mux-clockQRSTUV auxclkreq5_ck@224~ ti,mux-clockQRSTUV$clockdomainsscm@c000ti,omap4-scm-wkupctrl_module_wkuppadconf@1e000%ti,omap4-scm-padconf-wkupsimple-bus+ wctrl_module_pad_wkuppinmux@40 ti,omap4-padconfpinctrl-single@8+j<'ypinmux_usb_gpio_mux_sel2_pins npinmux_vibrator_direction_pinWpinmux_vibrator_enable_pinYocmcram@40304000 mmio-sram@0@dma-controller@4a056000ti,omap4430-sdmaJ`0g   & dma_system^gpio@4a310000ti,omap4-gpioJ1 ggpio13EU'<hgpio@48055000ti,omap4-gpioHP ggpio2EU'<ggpio@48057000ti,omap4-gpioHp ggpio3EU'<lgpio@48059000ti,omap4-gpioH g gpio4EU'<xgpio@4805b000ti,omap4-gpioH g!gpio5EU'<gpio@4805d000ti,omap4-gpioH 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compatibleinterrupt-parent#address-cells#size-cellsmodelstdout-pathi2c0i2c1i2c2i2c3serial0serial1serial2serial3display0display1device_typenext-level-cacheregclocksclock-namesclock-latencyoperating-pointscooling-min-levelcooling-max-level#cooling-cellsphandleti,hwmodsinterrupt-controller#interrupt-cellscache-unifiedcache-levelinterruptssramranges#clock-cellsclock-frequencyti,bit-shiftti,max-divti,autoidle-shiftti,index-starts-at-oneti,invert-autoidle-bitclock-multclock-divti,index-power-of-twoassigned-clocksassigned-clock-ratesti,dividersti,clock-divti,clock-mult#pinctrl-cellspinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsgpio-hoggpiosoutput-highline-namepinctrl-namespinctrl-0#pwm-cellsti,timersti,clock-sourcepwmspwm-namesdirection-duty-cycle-nsreg-namesti,sysc-maskti,sysc-sidlestatusdmasdma-namesgpmc,num-csgpmc,num-waitpinsti,no-idle-on-initinterrupts-extendedenable-gpiosmax-speed#hwlock-cellsinterrupt-nameswakeup-sourceled-sourcesramp-up-msecramp-down-msecvdd-supplyrotation-matrixti,spi-num-csspi-max-frequencyspi-cs-high#io-channel-cellsio-channelsio-channel-namespower-suppliesmode-gpiosregulator-enable-ramp-delayregulator-boot-onregulator-always-onregulator-initial-modepinctrl-1pinctrl-2pinctrl-3#phy-cellsvusb-supplylabelti,dual-voltti,needs-special-resetpbias-supplyvmmc-supplybus-widthcd-gpiosnon-removablecap-power-off-cardref-clock-frequencytcxo-clock-frequency#iommu-cellsti,sysc-midleti,sysc-delay-usti,iommu-bus-err-backti,buffer-sizekeypad,num-rowskeypad,num-columnslinux,keymapphy-typehw-caps-read-idle-ctrlhw-caps-ll-interfacehw-caps-temp-alertctrl-module#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,timer-alwonti,timer-dspti,timer-pwmport1-modeport2-moderemote-wakeup-connectedphysusb-phyphy-namesmultipointnum-epsram-bitsinterface-typepowerti,tranxdone-status-maskti,settling-timeti,clock-cyclesti,abb_inforemote-endpointlanesvddi-supplyreset-gpioswidth-mmheight-mmbacklighthback-porchhactivehfront-porchhsync-lenvback-porchvactivevfront-porchvsync-lenhsync-activevsync-activede-activepixelclk-activevdda-supply#thermal-sensor-cellspolling-delay-passivepolling-delaythermal-sensorscoefficientstemperaturehysteresistripcooling-devicehpd-gpiosgpioenable-active-highvin-supplystartup-delay-uslinux,codelinux,can-disablelinux,input-type