╨ ■э╘<8╩а( Ь╩hti,omap4430ti,omap4+chosen7/ocp/serial@48020000aliasesC/ocp/i2c@48070000H/ocp/i2c@48072000M/ocp/i2c@48060000R/ocp/i2c@48350000W/ocp/serial@4806a000_/ocp/serial@4806c000g/ocp/serial@48020000o/ocp/serial@4806e000w/connector0А/connector17Й/ocp/usbhshost@4a064000/ehci@4a064c00/hub@1/usbether@1cpus+cpu@0arm,cortex-a9ТcpuЮп│║cpu╞Ур ╘Ургш '└OА5шaА√хў Зcpu@1arm,cortex-a9ТcpuЮпpmuarm,cortex-a9-pmu debugssinterrupt-controller@48241000arm,cortex-a9-gic*?пH$H$l2-cache-controller@48242000arm,pl310-cacheпH$ P^local-timer@48240600arm,cortex-a9-twd-timer│пH$ j interrupt-controller@48281000ti,omap4-wugen-mpu*?пH(socti,omap-inframpu ti,omap4-mpu mpuudsp ti,omap3-c64 dspiva ti,ivahd ivaocpti,omap4-l3-nocsimple-bus+z l3_main_1l3_main_2l3_main_3пDDА Ej l4@4a000000ti,omap4-l4-cfgsimple-bus+zJcm1@4000ti,omap4-cm1simple-busп@ +z@ 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$,(dpll_core_x2_ckБti,omap4-dpll-x2-clock│dpll_core_m6x2_ck@140Бti,divider-clock│л╢п@╚▀dpll_core_m2_ck@130Бti,divider-clock│л╢п0╚▀ddrphy_ckБfixed-factor-clock│Ўdpll_core_m5x2_ck@13cБti,divider-clock│л╢п<╚▀div_core_ck@100Бti,divider-clock│плdiv_iva_hs_clk@1dcБti,divider-clock│лп▄div_mpu_hs_clk@19cБti,divider-clock│лпЬdpll_core_m4x2_ck@138Бti,divider-clock│л╢п8╚▀dll_clk_div_ckБfixed-factor-clock│Ўdpll_abe_m2_ck@1f0Бti,divider-clock│лпЁ╚"dpll_core_m3x2_gate_ck@134Б ti,composite-no-wait-gate-clock│Юп4dpll_core_m3x2_div_ck@134Бti,composite-divider-clock│лп4╚dpll_core_m3x2_ckБti,composite-clock│Bdpll_core_m7x2_ck@144Бti,divider-clock│л╢пD╚▀iva_hsd_byp_clk_mux_ck@1acБ ti,mux-clock│Юпмdpll_iva_ck@1a0Бti,omap4-dpll-clock│падми!17А№dpll_iva_x2_ckБti,omap4-dpll-x2-clock│dpll_iva_m4x2_ck@1b8Бti,divider-clock│л╢п╕╚▀!1└~dpll_iva_m5x2_ck@1bcБti,divider-clock│л╢п╝╚▀!1▄] dpll_mpu_ck@160Бti,omap4-dpll-clock│п`dlhdpll_mpu_m2_ck@170Бti,divider-clock│л╢пp╚▀per_hs_clk_div_ckБfixed-factor-clock│Ў#usb_hs_clk_div_ckБfixed-factor-clock│Ў)l3_div_ck@100Бti,divider-clock│Юлп l4_div_ck@100Бti,divider-clock│ Юлпlp_clk_div_ckБfixed-factor-clock│ Ў>mpu_periphclkБfixed-factor-clock│Ўocp_abe_iclk@528Бti,divider-clock│!Юп(Fper_abe_24m_fclkБfixed-factor-clock│"Ўdummy_ckБfixed-clockОclockdomainsmpuss_cm@300ti,omap4-cmп+zclk@20ti,clkctrlп Бtesla_cm@400ti,omap4-cmп+zclk@20ti,clkctrlп Бabe_cm@500ti,omap4-cmп+zclk@20ti,clkctrlп lБ!cm2@8000ti,omap4-cm2simple-busпА0+zА0clocks+per_hsd_byp_clk_mux_ck@14cБ ti,mux-clock│#ЮпL$dpll_per_ck@140Бti,omap4-dpll-clock│$п@DLH%dpll_per_m2_ck@150Бti,divider-clock│%лпP╚-dpll_per_x2_ck@150Бti,omap4-dpll-x2-clock│%пP&dpll_per_m2x2_ck@150Бti,divider-clock│&л╢пP╚▀,dpll_per_m3x2_gate_ck@154Б ti,composite-no-wait-gate-clock│&ЮпT'dpll_per_m3x2_div_ck@154Бti,composite-divider-clock│&лпT╚(dpll_per_m3x2_ckБti,composite-clock│'(Cdpll_per_m4x2_ck@158Бti,divider-clock│&л╢пX╚▀.dpll_per_m5x2_ck@15cБti,divider-clock│&л╢п\╚▀dpll_per_m6x2_ck@160Бti,divider-clock│&л╢п`╚▀+dpll_per_m7x2_ck@164Бti,divider-clock│&л╢пd╚▀dpll_usb_ck@180Бti,omap4-dpll-j-type-clock│)пАДМИ*dpll_usb_clkdcoldo_ck@1b4Бti,fixed-factor-clock│*R╢п┤_▀dpll_usb_m2_ck@190Бti,divider-clock│*л╢пР╚▀/ducati_clk_mux_ck@100Б ti,mux-clock│+пfunc_12m_fclkБfixed-factor-clock│,Ўfunc_24m_clkБfixed-factor-clock│-Ўfunc_24mc_fclkБfixed-factor-clock│,Ўfunc_48m_fclk@108Бti,divider-clock│,пFfunc_48mc_fclkБfixed-factor-clock│,Ўfunc_64m_fclk@108Бti,divider-clock│.пFfunc_96m_fclk@108Бti,divider-clock│,пFinit_60m_fclk@104Бti,divider-clock│/пFyper_abe_nc_fclk@108Бti,divider-clock│"плsha2md5_fck@15c8Бti,gate-clock│ Юп╚usb_phy_cm_clk32k@640Бti,gate-clock│0Юп@wclockdomainsl3_init_clkdmti,clockdomain│*l4_ao_cm@600ti,omap4-cmп+zclk@20ti,clkctrlп Б_l3_1_cm@700ti,omap4-cmп+zclk@20ti,clkctrlп Бl3_2_cm@800ti,omap4-cmп+zclk@20ti,clkctrlп Бducati_cm@900ti,omap4-cmп +z clk@20ti,clkctrlп Бl3_dma_cm@a00ti,omap4-cmп +z clk@20ti,clkctrlп Бl3_emif_cm@b00ti,omap4-cmп+zclk@20ti,clkctrlп Бd2d_cm@c00ti,omap4-cmп+zclk@20ti,clkctrlп Бl4_cfg_cm@d00ti,omap4-cmп +z clk@20ti,clkctrlп Бl3_instr_cm@e00ti,omap4-cmп+zclk@20ti,clkctrlп $Бivahd_cm@f00ti,omap4-cmп+zclk@20ti,clkctrlп Бiss_cm@1000ti,omap4-cmп+zclk@20ti,clkctrlп Бql3_dss_cm@1100ti,omap4-cmп+zclk@20ti,clkctrlп БАl3_gfx_cm@1200ti,omap4-cmп+zclk@20ti,clkctrlп Бl3_init_cm@1300ti,omap4-cmп+zclk@20ti,clkctrlп ─Бpl4_per_cm@1400ti,omap4-cmп+zclk@20ti,clkctrlп DБ\scm@2000ti,omap4-scm-coresimple-busп +z ctrl_module_corescm_conf@0sysconп+scm@100000%ti,omap4-scm-padconf-coresimple-busп+z ctrl_module_pad_corepinmux@40 ti,omap4-padconfpinctrl-singleп@Ц+m?*|Ъ ╖default┼12345^pinmux_twl6040_pins╧р`dpinmux_mcpdm_pins(╧╞╚╩╠╬rpinmux_mcbsp1_pins ╧╛└┬─tpinmux_dss_dpi_pinsр╧"$&(*,.0246tvxz|~АВДЖИКМОРТФ1pinmux_tfp410_pins╧D2pinmux_dss_hdmi_pins╧Z\^3pinmux_tpd12s015_pins╧"HX4pinmux_hsusbb1_pins`╧ВДЖИКМОРТФЦШ5pinmux_i2c1_pins╧тф`pinmux_i2c2_pins╧цшhpinmux_i2c3_pins╧ъьipinmux_i2c4_pins╧юЁjpinmux_wl12xx_gpio ╧&,02Мpinmux_wl12xx_pins@╧8: mpinmux_twl6030_pins╧^Aaomap4_padconf_global@5a0sysconsimple-busпаp+zаp6pbias_regulator@60ti,pbias-omap4ti,pbias-omapп`у6pbias_mmc_omap4ъpbias_mmc_omap4∙w@-╞└kl4@300000ti,omap4-l4-wkupsimple-bus+z0counter@4000ti,omap-counter32kп@ counter_32kprm@6000 ti,omap4-prmп`0j+z`0clocks+sys_clkin_ck@110Б ti,mux-clock│789:;<=п╚abe_dpll_bypass_clk_mux_ck@108Б ti,mux-clock│0Юп abe_dpll_refclk_mux_ck@10cБ ti,mux-clock│0п dbgclk_mux_ckБfixed-factor-clock│Ўl4_wkup_clk_mux_ck@108Б ti,mux-clock│>пsyc_clk_div_ck@100Бti,divider-clock│плusim_ck@1858Бti,divider-clock│.ЮпXF?usim_fclk@1858Бti,gate-clock│?ЮпXtrace_clk_div_ckБti,clkdm-gate-clock│@Abandgap_fclk@1888Бti,gate-clock│0ЮпИclockdomainsemu_sys_clkdmti,clockdomain│Al4_wkup_cm@1800ti,omap4-cmп+zclk@20ti,clkctrlп \Бxemu_sys_cm@1a00ti,omap4-cmп+zclk@20ti,clkctrlп Б@scrm@a000ti,omap4-scrmпа clocks+auxclk0_src_gate_ck@310Б ti,composite-no-wait-gate-clock│BЮпDauxclk0_src_mux_ck@310Бti,composite-mux-clock│BCЮпEauxclk0_src_ckБti,composite-clock│DEFauxclk0_ck@310Бti,divider-clock│FЮлпVauxclk1_src_gate_ck@314Б ti,composite-no-wait-gate-clock│BЮпGauxclk1_src_mux_ck@314Бti,composite-mux-clock│BCЮпHauxclk1_src_ckБti,composite-clock│GHIauxclk1_ck@314Бti,divider-clock│IЮлпWauxclk2_src_gate_ck@318Б ti,composite-no-wait-gate-clock│BЮпJauxclk2_src_mux_ck@318Бti,composite-mux-clock│BCЮпKauxclk2_src_ckБti,composite-clock│JKLauxclk2_ck@318Бti,divider-clock│LЮлпXauxclk3_src_gate_ck@31cБ ti,composite-no-wait-gate-clock│BЮпMauxclk3_src_mux_ck@31cБti,composite-mux-clock│BCЮпNauxclk3_src_ckБti,composite-clock│MNOauxclk3_ck@31cБti,divider-clock│OЮлпYauxclk4_src_gate_ck@320Б ti,composite-no-wait-gate-clock│BЮп Pauxclk4_src_mux_ck@320Бti,composite-mux-clock│BCЮп Qauxclk4_src_ckБti,composite-clock│PQRauxclk4_ck@320Бti,divider-clock│RЮлп Zauxclk5_src_gate_ck@324Б ti,composite-no-wait-gate-clock│BЮп$Sauxclk5_src_mux_ck@324Бti,composite-mux-clock│BCЮп$Tauxclk5_src_ckБti,composite-clock│STUauxclk5_ck@324Бti,divider-clock│UЮлп$[auxclkreq0_ck@210Б ti,mux-clock│VWXYZ[Юпauxclkreq1_ck@214Б ti,mux-clock│VWXYZ[Юпauxclkreq2_ck@218Б ti,mux-clock│VWXYZ[Юпauxclkreq3_ck@21cБ ti,mux-clock│VWXYZ[Юпauxclkreq4_ck@220Б ti,mux-clock│VWXYZ[Юп auxclkreq5_ck@224Б ti,mux-clock│VWXYZ[Юп$clockdomainsscm@c000ti,omap4-scm-wkupп└ ctrl_module_wkuppadconf@1e000%ti,omap4-scm-padconf-wkupsimple-busпр+zр ctrl_module_pad_wkuppinmux@40 ti,omap4-padconfpinctrl-singleп@8+m?*|Ъ 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compatibleinterrupt-parent#address-cells#size-cellsstdout-pathi2c0i2c1i2c2i2c3serial0serial1serial2serial3display0display1ethernetdevice_typenext-level-cacheregclocksclock-namesclock-latencyoperating-pointscooling-min-levelcooling-max-level#cooling-cellsphandleti,hwmodsinterrupt-controller#interrupt-cellscache-unifiedcache-levelinterruptssramranges#clock-cellsclock-frequencyti,bit-shiftti,max-divti,autoidle-shiftti,index-starts-at-oneti,invert-autoidle-bitclock-multclock-divti,index-power-of-twoassigned-clocksassigned-clock-ratesti,dividersti,clock-divti,clock-mult#pinctrl-cellspinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsreg-namesti,sysc-maskti,sysc-sidlestatusdmasdma-namesgpmc,num-csgpmc,num-waitpinsti,no-idle-on-initinterrupts-extended#hwlock-cellsregulator-always-onusb-supply#pwm-cells#io-channel-cellsti,audpwron-gpiovio-supplyv2v1-supplyenable-active-highti,spi-num-csti,dual-voltti,needs-special-resetpbias-supplyvmmc-supplybus-widthnon-removablecap-power-off-cardref-clock-frequencyinterrupt-names#iommu-cellsti,sysc-midleti,sysc-delay-usti,iommu-bus-err-backti,buffer-sizephy-typehw-caps-read-idle-ctrlhw-caps-ll-interfacehw-caps-temp-alertcs1-useddevice-handlectrl-module#phy-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,timer-alwonti,timer-dspti,timer-pwmport1-moderemote-wakeup-connectedphysusb-phyphy-namesmultipointnum-epsram-bitsinterface-typepowerti,tranxdone-status-maskti,settling-timeti,clock-cyclesti,abb_infovdd-supplyvdda-supplyremote-endpointdata-lines#thermal-sensor-cellspolling-delay-passivepolling-delaythermal-sensorscoefficientstemperaturehysteresistripcooling-devicedensityio-widthtRPab-min-tcktRCD-min-tcktWR-min-tcktRASmin-min-tcktRRD-min-tcktWTR-min-tcktXP-min-tcktRTP-min-tcktCKE-min-tcktCKESR-min-tcktFAW-min-tckmin-freqmax-freqtRPabtRCDtWRtRAS-mintRRDtWTRtXPtRTPtCKESRtDQSCK-maxtFAWtZQCStZQCLtZQinittRAS-max-nstDQSCK-max-deratedlabelgpioslinux,default-triggerti,modelti,mclk-freqti,mcpdmti,twl6040ti,audio-routingstartup-delay-usregulator-boot-onreset-gpiosvcc-supplypowerdown-gpiosdigitalddc-i2c-bus