Ð þíÖ@8Íœ(¤ÍdCvariscite,var-dvk-om44variscite,var-som-om44ti,omap4460ti,omap4 +7Variscite VAR-DVK-OM44chosenaliases=/ocp/i2c@48070000B/ocp/i2c@48072000G/ocp/i2c@48060000L/ocp/i2c@48350000Q/ocp/serial@4806a000Y/ocp/serial@4806c000a/ocp/serial@48020000i/ocp/serial@4806e000 q/display z/connectorcpus+cpu@0arm,cortex-a9ƒcpu ¤«cpu·“àÅW0£è ®`O€ ÀèÖèú cpu@1arm,cortex-a9ƒcpu pmuarm,cortex-a9-pmudebugss67interrupt-controller@48241000arm,cortex-a9-gic&; H$H$  l2-cache-controller@48242000arm,pl310-cache H$ LZ local-timer@48240600arm,cortex-a9-twd-timer¤ H$    interrupt-controller@48281000ti,omap4-wugen-mpu&; H(  socti,omap-inframpu ti,omap4-mpumpufdsp ti,omap3-c64dspiva ti,ivahdivaocpti,omap4-l3-nocsimple-bus+kl3_main_1l3_main_2l3_main_3 DD€ E  l4@4a000000ti,omap4-l4-cfgsimple-bus+ kJcm1@4000ti,omap4-cm1simple-bus @ + k@ clocks+extalt_clkin_ckr fixed-clock„DÀpad_clks_src_ckr fixed-clock· pad_clks_ck@108rti,gate-clock¤ pad_slimbus_core_clks_ckr fixed-clock·secure_32k_clk_src_ckr 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>bandgap_ts_fclk@1888rti,gate-clock¤> ˆclockdomainsemu_sys_clkdmti,clockdomain¤?l4_wkup_cm@1800 ti,omap4-cm + kclk@20 ti,clkctrl  \r ~emu_sys_cm@1a00 ti,omap4-cm + kclk@20 ti,clkctrl  r <scrm@a000ti,omap4-scrm   clocks+auxclk0_src_gate_ck@310r ti,composite-no-wait-gate-clock¤@  Bauxclk0_src_mux_ck@310rti,composite-mux-clock ¤@A  Cauxclk0_src_ckrti,composite-clock¤BC Dauxclk0_ck@310rti,divider-clock¤Dœ  Tauxclk1_src_gate_ck@314r ti,composite-no-wait-gate-clock¤@  Eauxclk1_src_mux_ck@314rti,composite-mux-clock ¤@A  Fauxclk1_src_ckrti,composite-clock¤EF Gauxclk1_ck@314rti,divider-clock¤Gœ  Uauxclk2_src_gate_ck@318r ti,composite-no-wait-gate-clock¤@  Hauxclk2_src_mux_ck@318rti,composite-mux-clock ¤@A  Iauxclk2_src_ckrti,composite-clock¤HI Jauxclk2_ck@318rti,divider-clock¤Jœ  Vauxclk3_src_gate_ck@31cr ti,composite-no-wait-gate-clock¤@  Kauxclk3_src_mux_ck@31crti,composite-mux-clock ¤@A  Lauxclk3_src_ckrti,composite-clock¤KL Mauxclk3_ck@31crti,divider-clock¤Mœ  Wauxclk4_src_gate_ck@320r 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