G8(%amarula,vyasa-rk3288rockchip,rk3288&7Amarula Vyasa-RK3288aliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/dwmmc@ff0f0000k/dwmmc@ff0c0000q/dwmmc@ff0d0000w/dwmmc@ff0e0000}/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000arm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12`@p@ @OOa sB@ ~ ' 9  K 0 $@29Ecpu@501cpuarm,cortex-a12Ecpu@502cpuarm,cortex-a12Ecpu@503cpuarm,cortex-a12Eamba simple-busMdma-controller@ff250000arm,pl330arm,primecell%@T_2 zapb_pclkEdma-controller@ff600000arm,pl330arm,primecell`@T_2 zapb_pclk disableddma-controller@ffb20000arm,pl330arm,primecell@T_2 zapb_pclkETreserved-memoryMdma-unusable@fe000000oscillator fixed-clockn6xin24mE timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer  H 2 a ztimerpclkdisplay-subsystemrockchip,display-subsystem dwmmc@ff0c0000rockchip,rk3288-dw-mshcр 2Drvzbiuciuciu-driveciu-sample  @resetokay (9KVdefaultd nzdwmmc@ff0d0000rockchip,rk3288-dw-mshcр 2Eswzbiuciuciu-driveciu-sample ! @reset disableddwmmc@ff0e0000rockchip,rk3288-dw-mshcр 2Ftxzbiuciuciu-driveciu-sample "@reset disableddwmmc@ff0f0000rockchip,rk3288-dw-mshcр 2Guyzbiuciuciu-driveciu-sample #@reset disabledsaradc@ff100000rockchip,saradc $2I[zsaradcapb_pclkW saradc-apb disabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi2ARzspiclkapb_pclk  txrx ,Vdefaultd disabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi2BSzspiclkapb_pclk txrx -Vdefaultd disabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi2CTzspiclkapb_pclktxrx .Vdefaultd disabledi2c@ff140000rockchip,rk3288-i2c >zi2c2MVdefaultd disabledi2c@ff150000rockchip,rk3288-i2c ?zi2c2OVdefaultd  disabledi2c@ff160000rockchip,rk3288-i2c @zi2c2PVdefaultd! disabledi2c@ff170000rockchip,rk3288-i2c Azi2c2QVdefaultd" disabledserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 72MUzbaudclkapb_pclkVdefaultd# disabledserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 82NVzbaudclkapb_pclkVdefaultd$ disabledserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 92OWzbaudclkapb_pclkVdefaultd%okayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart :2PXzbaudclkapb_pclkVdefaultd& disabledserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ;2QYzbaudclkapb_pclkVdefaultd' disabledthermal-zonesreserve_thermal(cpu_thermald(tripscpu_alert0ppassiveE)cpu_alert1$passiveE*cpu_crit_ criticalcooling-mapsmap0 ) map1 * gpu_thermald(tripsgpu_alert0ppassiveE+gpu_crit_ criticalcooling-mapsmap0 + tsadc@ff280000rockchip,rk3288-tsadc( %2HZztsadcapb_pclk tsadc-apbVinitdefaultsleepd,-(,2Hsokay_vE(ethernet@ff290000rockchip,rk3288-gmac)macirqeth_wake_irq.82fgc]Mzstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macB stmmacethokay/inputVdefaultd01234rgmii  'B@ !510:usb@ff500000 generic-ehciP 2zusbhostC6Husbokayusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T 2zotgRhostC7 Husb2-phyokayVdefaultd8usb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X 2zotgRotgZl{@@ C9 Husb2-phyokayusb@ff5c0000 generic-ehci\ 2zusbhost disabledi2c@ff650000rockchip,rk3288-i2ce <zi2c2LVdefaultd:okaypmic@1brockchip,rk808&;xin32krk808-clkout2Vdefaultd<=>>>>>>? >>&>3?regulatorsDCDC_REG1@vdd_armO qgpEregulator-state-memDCDC_REG2@vdd_gpuO PgEnregulator-state-memB@DCDC_REG3@vcc_ddrregulator-state-memDCDC_REG4@vcc_ioO2Zg2ZE?regulator-state-mem2ZLDO_REG1@vcc_tpO2Zg2Zregulator-state-mem2ZLDO_REG2 @vcc_codecO2Zg2Zregulator-state-memLDO_REG3@vdd_10OB@gB@regulator-state-memB@LDO_REG4@vcc_gpsOw@gw@regulator-state-memw@LDO_REG5 @vccio_sdOw@g2ZEregulator-state-mem2ZLDO_REG6 @vcc10_lcdOB@gB@regulator-state-memw@LDO_REG7@vcc_18Ow@gw@ESregulator-state-memw@LDO_REG8 @vcc18_lcdOw@gw@regulator-state-memw@SWITCH_REG1@vcc_sdO2Zg2ZEregulator-state-memSWITCH_REG2@vcc_lanO2Zg2ZE4regulator-state-memi2c@ff660000rockchip,rk3288-i2cf =zi2c2NVdefaultd@okayEjpwm@ff680000rockchip,rk3288-pwmhVdefaultdA2^zpwm disabledpwm@ff680010rockchip,rk3288-pwmhVdefaultdB2^zpwm disabledpwm@ff680020rockchip,rk3288-pwmh VdefaultdC2^zpwm disabledpwm@ff680030rockchip,rk3288-pwmh0VdefaultdD2^zpwm disabledbus_intmem@ff700000 mmio-srampMpsmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdsEpower-controller!rockchip,rk3288-power-controllerh EWpd_vio@9 2chgfdehilkj$EFGHIJKLMpd_hevc@11 2opNOpd_video@12 2Ppd_gpu@13 2QRreboot-modesyscon-reboot-modeRB+RB9RB IRBsyscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruv.UHjk$b#gׄeрxhрxhEsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfdwE.edp-phyrockchip,rk3288-dp-phy2hz24mw disabledEgio-domains"rockchip,rk3288-io-voltage-domainokayS??S4???Susbphyrockchip,rk3288-usb-phyokayusb-phy@320w 2]zphyclkE9usb-phy@334w42^zphyclkE6usb-phy@348wH2_zphyclkE7watchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt2p Ookaysound@ff88b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif zhclkmclk2TTtx 6VdefaultdU. disabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s 5TTtxrxzi2s_hclki2s_clk2RVdefaultdV) disabledcypto-controller@ff8a0000rockchip,rk3288-crypto@ 0 2}zaclkhclksclkapb_pclk crypto-rstokayiommu@ff900800rockchip,iommu@ iep_mmuC disablediommu@ff914000rockchip,iommu @P isp_mmuCP disabledrga@ff920000rockchip,rk3288-rga 2jzaclkhclksclkkW ilm coreaxiahbvop@ff930000rockchip,rk3288-vop 2zaclk_vopdclk_vophclk_vopkW def axiahbdclkyXokayportE endpoint@0YEkendpoint@1ZEhendpoint@2[Ebendpoint@3\Eeiommu@ff930300rockchip,iommu  vopb_mmukW CokayEXvop@ff940000rockchip,rk3288-vop 2zaclk_vopdclk_vophclk_vopkW  axiahbdclky]okayportE endpoint@0^Elendpoint@1_Eiendpoint@2`Ecendpoint@3aEfiommu@ff940300rockchip,iommu  vopl_mmukW CokayE]mipi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi@ 2~d zrefpclkkW . disabledportsportendpoint@0bE[endpoint@1cE`lvds@ff96c000rockchip,rk3288-lvds@2g zpclk_lvdsVlcdcddkW . disabledportsport@0endpoint@0eE\endpoint@1fEadp@ff970000rockchip,rk3288-dp@ b2iczdppclkCgHdpodp. disabledportsport@0endpoint@0hEZendpoint@1iE_hdmi@ff980000rockchip,rk3288-dw-hdmi. g2hmnziahbisfrceckW okayjportsportendpoint@0kEYendpoint@1lE^iommu@ff9a0800rockchip,iommu vpu_mmuC disablediommu@ff9c0440rockchip,iommu @@@ o hevc_mmuC disabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760$ jobmmugpu2mkW okayngpu-opp-tableoperating-points-v2Emopp@100000000~opp@200000000 ~opp@300000000B@opp@400000000ׄopp@500000000eOopp@600000000#Fqos@ffaa0000syscon EQqos@ffaa0080syscon ERqos@ffad0000syscon EFqos@ffad0100syscon EGqos@ffad0180syscon EHqos@ffad0400syscon EIqos@ffad0480syscon EJqos@ffad0500syscon EEqos@ffad0800syscon EKqos@ffad0880syscon ELqos@ffad0900syscon EMqos@ffae0000syscon EPqos@ffaf0000syscon ENqos@ffaf0080syscon EOinterrupt-controller@ffc01000 arm,gic-400@ @ `   Eefuse@ffb40000rockchip,rk3288-efuse 2q zpclk_efusecpu_leakage@17pinctrlrockchip,rk3288-pinctrl.Mgpio0@ff750000rockchip,gpio-banku Q2@E;gpio1@ff780000rockchip,gpio-bankx R2Agpio2@ff790000rockchip,gpio-banky S2Bgpio3@ff7a0000rockchip,gpio-bankz T2Cgpio4@ff7b0000rockchip,gpio-bank{ U2DE5gpio5@ff7c0000rockchip,gpio-bank| V2Egpio6@ff7d0000rockchip,gpio-bank} W2Fgpio7@ff7e0000rockchip,gpio-bank~ X2Ggpio8@ff7f0000rockchip,gpio-bank Y2HEwhdmihdmi-cec-c0ohdmi-cec-c7ohdmi-ddc oopcfg-pull-up!Eppcfg-pull-down.Eqpcfg-pull-none=Eopcfg-pull-none-12ma=J Ersleepglobal-pwroffoE=ddrio-pwroffoddr0-retentionpddr1-retentionpedpedp-hpd qi2c0i2c0-xfer ooE:i2c1i2c1-xfer ooEi2c2i2c2-xfer  o oE@i2c3i2c3-xfer ooE i2c4i2c4-xfer ooE!i2c5i2c5-xfer ooE"i2s0i2s0-bus`ooooooEVlcdclcdc-ctl@ooooEdsdmmcsdmmc-clkoE sdmmc-cmdpE sdmmc-cdpEsdmmc-bus1psdmmc-bus4@ppppEsdio0sdio0-bus1psdio0-bus4@ppppsdio0-cmdpsdio0-clkosdio0-cdpsdio0-wppsdio0-pwrpsdio0-bkpwrpsdio0-intpsdio1sdio1-bus1psdio1-bus4@ppppsdio1-cdpsdio1-wppsdio1-bkpwrpsdio1-intpsdio1-cmdpsdio1-clkosdio1-pwr pemmcemmc-clkoemmc-cmdpemmc-pwr pemmc-bus1pemmc-bus4@ppppemmc-bus8ppppppppspi0spi0-clk pEspi0-cs0 pEspi0-txpEspi0-rxpEspi0-cs1pspi1spi1-clk pEspi1-cs0 pEspi1-rxpEspi1-txpEspi2spi2-cs1pspi2-clkpEspi2-cs0pEspi2-rxpEspi2-tx pEuart0uart0-xfer poE#uart0-ctspuart0-rtsouart1uart1-xfer p oE$uart1-cts puart1-rts ouart2uart2-xfer poE%uart3uart3-xfer poE&uart3-cts puart3-rts ouart4uart4-xfer  p oE'uart4-ctspuart4-rtsotsadcotp-gpio oE,otp-out oE-pwm0pwm0-pinoEApwm1pwm1-pinoEBpwm2pwm2-pinoECpwm3pwm3-pinoEDgmacrgmii-pinsoooorrrrooo rrooE0rmii-pinsoooooooooophy-int pE3phy-pmebpE2phy-rstsE1spdifspdif-tx oEUpcfg-output-highYEspmicpmic-intpE<usb_hostphy-pwr-en sE8usb2-pwr-en oExusb_otgotg-vbus-drv oEuchosene/serial@ff690000memorymemorydc12-vbatregulator-fixed @dc12_vbatOgEtvboot-3v3regulator-fixed @vboot_3v3O2Zg2Zqtvsys-regulatorregulator-fixed@vcc_sysO8u g8u qtE>vboot-5vregulator-fixed @vboot_svOLK@gLK@qtv3g-3v3regulator-fixed@v3g_3v3O2Zg2Zqtvsus-5vregulator-fixed@vsus_5vOLK@gLK@q?Evvusb1-5vregulator-fixed @vusb1_5v| ,; VdefaultduOLK@gLK@qvvusb2-5vregulator-fixed @vusb2_5v| ,w VdefaultdxOLK@gLK@qvexternal-gmac-clock fixed-clocksY@ ext_gmacE/ #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points#cooling-cellsclock-latencyclockscpu0-supplyphandleranges#dma-cellsarm,pl330-broken-no-flushpclock-namesstatusclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredportsmax-frequencyfifo-depthreset-namesbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaydisable-wppinctrl-namespinctrl-0vmmc-supplyvqmmc-supply#io-channel-cellsdmasdma-namesreg-shiftreg-io-widthpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesrockchip,grfassigned-clocksassigned-clock-parentsclock_in_outphy-supplyphy-modesnps,reset-active-lowsnps,reset-delays-ussnps,reset-gpiotx_delayrx_delayphysphy-namesdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizerockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvolt#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsaudio-supplybb-supplydvp-supplyflash0-suuplyflash1-supplygpio30-supplygpio1830lcdc-supplysdcard-supplywifi-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointddc-i2c-busoperating-points-v2mali-supplyopp-hzopp-microvoltinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highstdout-pathvin-supplyenable-active-high