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hosclosc2allwinner,sun5i-a10s-ccuinterrupt-controller@1c204002allwinner,sun4i-a10-ic*pinctrl@1c20800c5apbhosclosc;*K2allwinner,sun5i-a10s-pinctrl emac0@0XWPD6PD7PD10PD11PD12PD13PD14PD15PD18PD19PD20PD21PD22PD23PD24PD25PD26PD27\emaci2c0@0WPB0PB1\i2c0i2c1@0 WPB15PB16\i2c1i2c2@0 WPB17PB18\i2c2ir0@0WPB4\ir0lcd_rgb565@0_WPD3PD4PD5PD6PD7PD10PD11PD12PD13PD14PD15PD19PD20PD21PD22PD23PD24PD25PD26PD27\lcd0lcd_rgb666@0hWPD2PD3PD4PD5PD6PD7PD10PD11PD12PD13PD14PD15PD18PD19PD20PD21PD22PD23PD24PD25PD26PD27\lcd0mmc0@0WPF0PF1PF2PF3PF4PF5\mmc0et mmc2@0.WPC6PC7PC8PC9PC10PC11PC12PC13PC14PC15\mmc2etmmc2-4bit@0WPC6PC7PC8PC9PC10PC11\mmc2etnand-base0@06WPC0PC1PC2PC5PC8PC9PC10PC11PC12PC13PC14PC15\nand0nand-cs@0WPC4\nand0nand-rb@0WPC6\nand0spi2@0 WPE1PE2PE3\spi2spi2-cs0@0WPE0\spi2uart1@0 WPE10PE11\uart1uart1@1WPG3PG4\uart1uart2@0WPD2PD3\uart2uart2-cts-rts@0WPD4PD5\uart2uart3@0 WPG9PG10\uart3uart3-cts-rts@0 WPG11PG12\uart3pwm0WPB2\pwmuart0@0 WPB19PB20\uart0uart2@1 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#address-cells#size-cellsinterrupt-parentmodelcompatiblerangesstdout-pathallwinner,pipelineclocksstatusethernet0serial0device_typereg#clock-cellsclock-frequencyclock-output-namesphandleinterrupts#dma-cellsclock-namesdmasdma-namesresetsremote-endpointallwinner,sramreset-namesallwinner,tcon-channelpinctrl-namespinctrl-0vmmc-supplybus-widthcd-gpioscd-invertednon-removablecap-sdio-irqinterrupt-namesphysphy-namesextcondr_mode#phy-cellsreg-namesusb0_id_det-gpiousb1_vbus-supply#reset-cellsinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellspinsfunctiondrive-strengthbias-pull-up#sound-dai-cells#thermal-sensor-cellsreg-shiftreg-io-widthassigned-clocksassigned-clock-rates#pwm-cellsallwinner,pipelinesregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-boot-onenable-active-highlabeldefault-state