8( Cvariscite,var-stk-om44variscite,var-som-om44ti,omap4460ti,omap4 +7Variscite VAR-STK-OM44chosenaliases=/ocp/i2c@48070000B/ocp/i2c@48072000G/ocp/i2c@48060000L/ocp/i2c@48350000Q/ocp/serial@4806a000Y/ocp/serial@4806c000a/ocp/serial@48020000i/ocp/serial@4806e000 q/connectorcpus+cpu@0arm,cortex-a9zcpucpuW0 `O cpu@1arm,cortex-a9zcpupmuarm,cortex-a9-pmudebugss67interrupt-controller@48241000arm,cortex-a9-gicH$H$ l2-cache-controller@48242000arm,pl310-cacheH$ -local-timer@48240600arm,cortex-a9-twd-timerH$    interrupt-controller@48281000ti,omap4-wugen-mpuH( socti,omap-inframpu ti,omap4-mpumpu9dsp ti,omap3-c64dspiva ti,ivahdivaocpti,omap4-l3-nocsimple-bus+>l3_main_1l3_main_2l3_main_3DD E  l4@4a000000ti,omap4-l4-cfgsimple-bus+ >Jcm1@4000ti,omap4-cm1simple-bus@ + >@ clocks+extalt_clkin_ckE fixed-clockRDpad_clks_src_ckE fixed-clockRpad_clks_ck@108Eti,gate-clockbpad_slimbus_core_clks_ckE fixed-clockRsecure_32k_clk_src_ckE fixed-clockRslimbus_src_clkE fixed-clockRslimbus_clk@108Eti,gate-clockb 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l4_div_ck@100Eti,divider-clock bolp_clk_div_ckEfixed-factor-clock :mpu_periphclkEfixed-factor-clockocp_abe_iclk@528Eti,divider-clock !b( per_abe_24m_fclkEfixed-factor-clock"dummy_ckE fixed-clockRclockdomainsmpuss_cm@300 ti,omap4-cm+ >clk@20 ti,clkctrl Etesla_cm@400 ti,omap4-cm+ >clk@20 ti,clkctrl Eabe_cm@500 ti,omap4-cm+ >clk@20 ti,clkctrl lE!cm2@8000ti,omap4-cm2simple-bus + > clocks+per_hsd_byp_clk_mux_ck@14cE ti,mux-clock#bL$dpll_per_ck@140Eti,omap4-dpll-clock$@DLH%dpll_per_m2_ck@150Eti,divider-clock%oP-dpll_per_x2_ck@150Eti,omap4-dpll-x2-clock%P&dpll_per_m2x2_ck@150Eti,divider-clock&ozP,dpll_per_m3x2_gate_ck@154E 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;usim_fclk@1858Eti,gate-clock;bXtrace_clk_div_ckEti,clkdm-gate-clock <?div_ts_ck@1888Eti,divider-clock=b   >bandgap_ts_fclk@1888Eti,gate-clock>bclockdomainsemu_sys_clkdmti,clockdomain?l4_wkup_cm@1800 ti,omap4-cm+ >clk@20 ti,clkctrl \E~emu_sys_cm@1a00 ti,omap4-cm+ >clk@20 ti,clkctrl E<scrm@a000ti,omap4-scrm clocks+auxclk0_src_gate_ck@310E ti,composite-no-wait-gate-clock@bBauxclk0_src_mux_ck@310Eti,composite-mux-clock @AbCauxclk0_src_ckEti,composite-clockBCDauxclk0_ck@310Eti,divider-clockDboTauxclk1_src_gate_ck@314E ti,composite-no-wait-gate-clock@bEauxclk1_src_mux_ck@314Eti,composite-mux-clock @AbFauxclk1_src_ckEti,composite-clockEFGauxclk1_ck@314Eti,divider-clockGboUauxclk2_src_gate_ck@318E ti,composite-no-wait-gate-clock@bHauxclk2_src_mux_ck@318Eti,composite-mux-clock @AbIauxclk2_src_ckEti,composite-clockHIJauxclk2_ck@318Eti,divider-clockJboVauxclk3_src_gate_ck@31cE ti,composite-no-wait-gate-clock@bKauxclk3_src_mux_ck@31cEti,composite-mux-clock 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@l]r]qqtxrxdes@480a5000 ti,omap4-desdesH P Rl]u]tqtxrxsham@4b100000ti,omap4-shamshamK 3l]wqrxregulator-abb-mpu ti,abb-v2abb_mpu+s2eokayJ0{J0`J"h'@base-addressint-addressefuse-addressxO1regulator-abb-iva ti,abb-v2abb_iva+s2eokayJ0{J0`J"h'@base-addressint-addressefuse-addressx~e  target-module@56000000ti,sysc-omap4ti,syscgpuVV @revsyscW fck+ >Vdss@58000000 ti,omap4-dssXeokay dss_core fck+>dispc@58001000ti,omap4-dispcX  dss_dispc fckencoder@58002000ti,omap4-rfbiX  edisabled dss_rfbi fckickencoder@58003000ti,omap4-vencX0 edisabled dss_venc fckencoder@58004000 ti,omap4-dsiX@XB@XC @protophypll 5 edisabled dss_dsi1  fcksys_clkencoder@58005000 ti,omap4-dsiXPXR@XS @protophypll T edisabled dss_dsi2  fcksys_clkencoder@58006000ti,omap4-hdmi X`XbXcXd@wppllphycore eeokay dss_hdmi  fcksys_clkl]L qaudio_tx{defaultportendpointbandgap@4a002260J"`J#,J#xti,omap4460-bandgap ~ thermal-zonescpu_thermal\۫tripscpu_alert,8passivecpu_crit,H8 criticalcooling-mapsmap0C Hmemory@80000000zmemory@soundti,abe-twl6040 WVAR-SOM-OM44`Imv{LHeadset StereophoneHSOLHeadset StereophoneHSORAFMLLine InAFMRLine Inhsusb1_phyusb-nop-xceiv{default gwW main_clkR$fixedregulator-vbatregulator-fixedVBAT2Z2Zwwl12xx_vmmc{defaultregulator-fixedvwl1271w@w@ u ptleds gpio-leds{defaultled0var:green:led0 g  heartbeatled1var:green:led1 g gpio-keys gpio-keys{default+user-key@184user gconnectorhdmi-connector{defaulthdmia uportendpoint compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2i2c3serial0serial1serial2serial3display0device_typenext-level-cacheregclocksclock-namesclock-latencyoperating-points#cooling-cellsphandleti,hwmodsinterruptsinterrupt-controller#interrupt-cellscache-unifiedcache-levelsramranges#clock-cellsclock-frequencyti,bit-shiftti,max-divti,autoidle-shiftti,index-starts-at-oneti,invert-autoidle-bitclock-multclock-divti,index-power-of-twoassigned-clocksassigned-clock-ratesti,dividersti,clock-divti,clock-mult#pinctrl-cellspinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsreg-namesti,sysc-maskti,sysc-sidlestatusdmasdma-namesgpmc,num-csgpmc,num-waitpinsti,no-idle-on-init#hwlock-cellsregulator-always-onusb-supply#pwm-cells#io-channel-cellsti,audpwron-gpiovio-supplyv2v1-supplyenable-active-highti,spi-num-csspi-max-frequencyti,dual-voltti,needs-special-resetpbias-supplyvmmc-supplybus-widthti,non-removablecap-power-off-cardref-clock-frequencycd-gpiosinterrupt-names#iommu-cellsti,sysc-midleti,sysc-delay-usti,iommu-bus-err-backti,buffer-sizephy-typehw-caps-read-idle-ctrlhw-caps-ll-interfacehw-caps-temp-alertctrl-module#phy-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,timer-alwonti,timer-dspti,timer-pwmport1-moderemote-wakeup-connectedphysusb-phyphy-namesmultipointnum-epsram-bitsinterface-typepowerti,tranxdone-status-maskti,settling-timeti,clock-cyclesti,abb_infovdda-supplyremote-endpoint#thermal-sensor-cellspolling-delay-passivepolling-delaythermal-sensorscoefficientstemperaturehysteresistripcooling-deviceti,modelti,mclk-freqti,mcpdmti,twl6040ti,audio-routingreset-gpiosvcc-supplyregulator-boot-onstartup-delay-uslabellinux,default-triggerlinux,codewakeup-sourcehpd-gpios