}8('rockchip,rk3288-fennecrockchip,rk3288&7Rockchip RK3288 Fennec Boardaliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/dwmmc@ff0f0000k/dwmmc@ff0c0000q/dwmmc@ff0d0000w/dwmmc@ff0e0000}/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000arm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12`@p@ @OOa sB@ ~ ' 9  K 0 $@29Ecpu@501cpuarm,cortex-a12Ecpu@502cpuarm,cortex-a12Ecpu@503cpuarm,cortex-a12Eamba simple-busMdma-controller@ff250000arm,pl330arm,primecell%@T_2 zapb_pclkEdma-controller@ff600000arm,pl330arm,primecell`@T_2 zapb_pclk disableddma-controller@ffb20000arm,pl330arm,primecell@T_2 zapb_pclkEQreserved-memoryMdma-unusable@fe000000oscillator fixed-clockn6xin24mE timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer  H 2 a ztimerpclkdisplay-subsystemrockchip,display-subsystem dwmmc@ff0c0000rockchip,rk3288-dw-mshcр 2Drvzbiuciuciu-driveciu-sample  @reset disableddwmmc@ff0d0000rockchip,rk3288-dw-mshcр 2Eswzbiuciuciu-driveciu-sample ! @reset disableddwmmc@ff0e0000rockchip,rk3288-dw-mshcр 2Ftxzbiuciuciu-driveciu-sample "@reset disableddwmmc@ff0f0000rockchip,rk3288-dw-mshcр 2Guyzbiuciuciu-driveciu-sample #@resetokay (3AdefaultO saradc@ff100000rockchip,saradc $Y2I[zsaradcapb_pclkW saradc-apb disabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi2ARzspiclkapb_pclkk  ptxrx ,AdefaultO disabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi2BSzspiclkapb_pclkk ptxrx -AdefaultO disabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi2CTzspiclkapb_pclkkptxrx .AdefaultO disabledi2c@ff140000rockchip,rk3288-i2c >zi2c2MAdefaultO disabledi2c@ff150000rockchip,rk3288-i2c ?zi2c2OAdefaultO disabledi2c@ff160000rockchip,rk3288-i2c @zi2c2PAdefaultO disabledi2c@ff170000rockchip,rk3288-i2c Azi2c2QAdefaultO  disabledserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 7z2MUzbaudclkapb_pclkAdefaultO! disabledserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 8z2NVzbaudclkapb_pclkAdefaultO" disabledserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 9z2OWzbaudclkapb_pclkAdefaultO#okayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart :z2PXzbaudclkapb_pclkAdefaultO$ disabledserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ;z2QYzbaudclkapb_pclkAdefaultO% disabledthermal-zonesreserve_thermal&cpu_thermald&tripscpu_alert0ppassiveE'cpu_alert1$passiveE(cpu_crit_ criticalcooling-mapsmap0' map1( gpu_thermald&tripsgpu_alert0ppassiveE)gpu_crit_ criticalcooling-mapsmap0) tsadc@ff280000rockchip,rk3288-tsadc( %2HZztsadcapb_pclk tsadc-apbAinitdefaultsleepO*+*s disabledE&ethernet@ff290000rockchip,rk3288-gmac)1macirqeth_wake_irqA,82fgc]Mzstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macB stmmacethokayN^-uinputAdefaultO./012rgmii 'B@ 30usb@ff500000 generic-ehciP 2zusbhost4usbokayusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T 2zotghost5 usb2-phyokayusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X 2zotgotg @@ 6 usb2-phyokayusb@ff5c0000 generic-ehci\ 2zusbhostokayi2c@ff650000rockchip,rk3288-i2ce <zi2c2LAdefaultO7okaypmic@1brockchip,rk808&8xin32krk808-clkout2AdefaultO9:*KY;e;q;};;;<<<<<<regulatorsDCDC_REG1 q+pCvdd_armEregulator-state-memRDCDC_REG2 P+Cvdd_gpuEjregulator-state-memkB@DCDC_REG3Cvcc_ddrregulator-state-memkDCDC_REG42Z+2ZCvcc_ioE<regulator-state-memk2ZLDO_REG12Z+2Z Cvccio_pmuregulator-state-memk2ZLDO_REG22Z+2ZCvcca_33regulator-state-memRLDO_REG3B@+B@Cvdd_10regulator-state-memkB@LDO_REG4w@+w@Cvcc_wlregulator-state-memkw@LDO_REG5w@+2Z Cvccio_sdregulator-state-memk2ZLDO_REG6B@+B@ Cvdd10_lcdregulator-state-memkB@LDO_REG7w@+w@Cvcc_18regulator-state-memkw@LDO_REG8w@+w@ Cvcc18_lcdregulator-state-memkw@SWITCH_REG1Cvcc_sdregulator-state-memkSWITCH_REG2Cvcc_lanE2regulator-state-memki2c@ff660000rockchip,rk3288-i2cf =zi2c2NAdefaultO= disabledpwm@ff680000rockchip,rk3288-pwmhAdefaultO>2^zpwm disabledpwm@ff680010rockchip,rk3288-pwmhAdefaultO?2^zpwm disabledpwm@ff680020rockchip,rk3288-pwmh AdefaultO@2^zpwm disabledpwm@ff680030rockchip,rk3288-pwmh0AdefaultOA2^zpwm disabledbus_intmem@ff700000 mmio-srampMpsmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdsEpower-controller!rockchip,rk3288-power-controllerNh^ ETpd_vio@9 2chgfdehilkj$BCDEFGHIJpd_hevc@11 2opKLpd_video@12 2Mpd_gpu@13 2NOreboot-modesyscon-reboot-modeRBRBRB RBsyscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruvA,HNjk$#gׄeрxhрxhEsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfdwE,edp-phyrockchip,rk3288-dp-phy2hz24m$ disabledEdio-domains"rockchip,rk3288-io-voltage-domain disabledusbphyrockchip,rk3288-usb-phyokayAdefaultOP /8usb-phy@320$ 2]zphyclkE6usb-phy@334$42^zphyclkE4usb-phy@348$H2_zphyclkE5watchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt2p O disabledsound@ff88b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif> zhclkmclk2TkQptx 6AdefaultORA, disabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s> 5kQQptxrxzi2s_hclki2s_clk2RAdefaultOSOj disabledcypto-controller@ff8a0000rockchip,rk3288-crypto@ 0 2}zaclkhclksclkapb_pclk crypto-rstokayiommu@ff900800rockchip,iommu@ 1iep_mmu2 zaclkiface disablediommu@ff914000rockchip,iommu @P 1isp_mmu2 zaclkiface disabledrga@ff920000rockchip,rk3288-rga 2jzaclkhclksclkT ilm coreaxiahbvop@ff930000rockchip,rk3288-vop 2zaclk_vopdclk_vophclk_vopT def axiahbdclkUokayportE endpoint@0VEgendpoint@1WEeendpoint@2XE_endpoint@3YEbiommu@ff930300rockchip,iommu  1vopb_mmu2 zaclkifaceT okayEUvop@ff940000rockchip,rk3288-vop 2zaclk_vopdclk_vophclk_vopT  axiahbdclkZokayportE endpoint@0[Ehendpoint@1\Efendpoint@2]E`endpoint@3^Eciommu@ff940300rockchip,iommu  1vopl_mmu2 zaclkifaceT okayEZmipi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi@ 2~d zrefpclkT A, disabledportsportendpoint@0_EXendpoint@1`E]lvds@ff96c000rockchip,rk3288-lvds@2g zpclk_lvdsAlcdcOaT A, disabledportsport@0endpoint@0bEYendpoint@1cE^dp@ff970000rockchip,rk3288-dp@ b2iczdppclkddpodpA, disabledportsport@0endpoint@0eEWendpoint@1fE\hdmi@ff980000rockchip,rk3288-dw-hdmi>A, g2hmnziahbisfrcecT okayportsportendpoint@0gEVendpoint@1hE[iommu@ff9a0800rockchip,iommu 1vpu_mmu2 zaclkiface disablediommu@ff9c0440rockchip,iommu @@@ o 1hevc_mmu2 zaclkiface disabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760$ 1jobmmugpu2iT okayjgpu-opp-tableoperating-points-v2Eiopp@100000000~opp@200000000 ~opp@300000000B@opp@400000000ׄopp@500000000eOopp@600000000#Fqos@ffaa0000syscon ENqos@ffaa0080syscon EOqos@ffad0000syscon ECqos@ffad0100syscon EDqos@ffad0180syscon EEqos@ffad0400syscon EFqos@ffad0480syscon EGqos@ffad0500syscon EBqos@ffad0800syscon EHqos@ffad0880syscon EIqos@ffad0900syscon EJqos@ffae0000syscon EMqos@ffaf0000syscon EKqos@ffaf0080syscon ELinterrupt-controller@ffc01000 arm,gic-400@ @ `   Eefuse@ffb40000rockchip,rk3288-efuse 2q zpclk_efusecpu_leakage@17pinctrlrockchip,rk3288-pinctrlA,Mgpio0@ff750000rockchip,gpio-banku Q2@,<E8gpio1@ff780000rockchip,gpio-bankx R2A,<gpio2@ff790000rockchip,gpio-banky S2B,<gpio3@ff7a0000rockchip,gpio-bankz T2C,<gpio4@ff7b0000rockchip,gpio-bank{ U2D,<E3gpio5@ff7c0000rockchip,gpio-bank| V2E,<gpio6@ff7d0000rockchip,gpio-bank} W2F,<gpio7@ff7e0000rockchip,gpio-bank~ X2G,<gpio8@ff7f0000rockchip,gpio-bank Y2H,<hdmihdmi-cec-c0Hkhdmi-cec-c7Hkhdmi-ddc Hkkpcfg-pull-upVElpcfg-pull-downcEmpcfg-pull-nonerEkpcfg-pull-none-12mar Ensleepglobal-pwroffHkE:ddrio-pwroffHkddr0-retentionHlddr1-retentionHledpedp-hpdH mi2c0i2c0-xfer HkkE7i2c1i2c1-xfer HkkEi2c2i2c2-xfer H k kE=i2c3i2c3-xfer HkkEi2c4i2c4-xfer HkkEi2c5i2c5-xfer HkkE i2s0i2s0-bus`HkkkkkkESlcdclcdc-ctl@HkkkkEasdmmcsdmmc-clkHksdmmc-cmdHlsdmmc-cdHlsdmmc-bus1Hlsdmmc-bus4@Hllllsdio0sdio0-bus1Hlsdio0-bus4@Hllllsdio0-cmdHlsdio0-clkHksdio0-cdHlsdio0-wpHlsdio0-pwrHlsdio0-bkpwrHlsdio0-intHlsdio1sdio1-bus1Hlsdio1-bus4@Hllllsdio1-cdHlsdio1-wpHlsdio1-bkpwrHlsdio1-intHlsdio1-cmdHlsdio1-clkHksdio1-pwrH lemmcemmc-clkHkE emmc-cmdHlE emmc-pwrH lEemmc-bus1Hlemmc-bus4@Hllllemmc-bus8HllllllllEspi0spi0-clkH lEspi0-cs0H lEspi0-txHlEspi0-rxHlEspi0-cs1Hlspi1spi1-clkH lEspi1-cs0H lEspi1-rxHlEspi1-txHlEspi2spi2-cs1Hlspi2-clkHlEspi2-cs0HlEspi2-rxHlEspi2-txH lEuart0uart0-xfer HlkE!uart0-ctsHluart0-rtsHkuart1uart1-xfer Hl kE"uart1-ctsH luart1-rtsH kuart2uart2-xfer HlkE#uart3uart3-xfer HlkE$uart3-ctsH luart3-rtsH kuart4uart4-xfer HlkE%uart4-ctsH luart4-rtsH ktsadcotp-gpioH kE*otp-outH kE+pwm0pwm0-pinHkE>pwm1pwm1-pinHkE?pwm2pwm2-pinHkE@pwm3pwm3-pinHkEAgmacrgmii-pinsHkkkknnnnkkk nnkkE.rmii-pinsHkkkkkkkkkkphy-intH lE1phy-pmebHlE0phy-rstHoE/spdifspdif-txH kERpcfg-output-highEopcfg-output-lowpcfg-pull-none-drv-8mapcfg-pull-up-drv-8maVpmicpmic-intHlE9usbphyhost-drvHkEPmemory@0memoryexternal-gmac-clock fixed-clocksY@ ext_gmacE-vsys-regulatorregulator-fixedCvcc_sysLK@+LK@E; #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points#cooling-cellsclock-latencyclockscpu0-supplyphandleranges#dma-cellsarm,pl330-broken-no-flushpclock-namesstatusclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredportsmax-frequencyfifo-depthreset-namesbus-widthcap-mmc-highspeeddisable-wpnon-removablepinctrl-namespinctrl-0#io-channel-cellsdmasdma-namesreg-shiftreg-io-widthpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-tempinterrupt-namesrockchip,grfassigned-clocksassigned-clock-parentsclock_in_outphy-supplyphy-modesnps,reset-active-lowsnps,reset-delays-ussnps,reset-gpiotx_delayrx_delayphysphy-namesdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizerockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvddio-supplyregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-nameregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvolt#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsvbus_drv-gpios#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointoperating-points-v2mali-supplyopp-hzopp-microvoltinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-low