T8(mqmaker,miqirockchip,rk3288& 7mqmaker MiQialiases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/dwmmc@ff0f0000k/dwmmc@ff0c0000q/dwmmc@ff0d0000w/dwmmc@ff0e0000}/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000arm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12`@p@ @OOa sB@ ~ ' 9  K 0 $@29Ecpu@501cpuarm,cortex-a12Ecpu@502cpuarm,cortex-a12Ecpu@503cpuarm,cortex-a12Eamba simple-busMdma-controller@ff250000arm,pl330arm,primecell%@T_2 zapb_pclkEdma-controller@ff600000arm,pl330arm,primecell`@T_2 zapb_pclk disableddma-controller@ffb20000arm,pl330arm,primecell@T_2 zapb_pclkEXreserved-memoryMdma-unusable@fe000000oscillator fixed-clockn6xin24mE timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer  H 2 a ztimerpclkdisplay-subsystemrockchip,display-subsystem dwmmc@ff0c0000rockchip,rk3288-dw-mshcр 2Drvzbiuciuciu-driveciu-sample  @resetokay (9KVdefaultd nzdwmmc@ff0d0000rockchip,rk3288-dw-mshcр 2Eswzbiuciuciu-driveciu-sample ! @reset disableddwmmc@ff0e0000rockchip,rk3288-dw-mshcр 2Ftxzbiuciuciu-driveciu-sample "@reset disableddwmmc@ff0f0000rockchip,rk3288-dw-mshcр 2Guyzbiuciuciu-driveciu-sample #@resetokay KVdefaultdnzsaradc@ff100000rockchip,saradc $2I[zsaradcapb_pclkW saradc-apbokayspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi2ARzspiclkapb_pclk  txrx ,Vdefaultd disabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi2BSzspiclkapb_pclk txrx -Vdefaultd ! disabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi2CTzspiclkapb_pclktxrx .Vdefaultd"#$% disabledi2c@ff140000rockchip,rk3288-i2c >zi2c2MVdefaultd&okayi2c@ff150000rockchip,rk3288-i2c ?zi2c2OVdefaultd' disabledi2c@ff160000rockchip,rk3288-i2c @zi2c2PVdefaultd(okayi2c@ff170000rockchip,rk3288-i2c Azi2c2QVdefaultd)okayEnserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 72MUzbaudclkapb_pclkVdefaultd* disabledserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 82NVzbaudclkapb_pclkVdefaultd+ disabledserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 92OWzbaudclkapb_pclkVdefaultd,okayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart :2PXzbaudclkapb_pclkVdefaultd-okayserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ;2QYzbaudclkapb_pclkVdefaultd. disabledthermal-zonesreserve_thermal/cpu_thermald/tripscpu_alert0 ppassiveE0cpu_alert1 $passiveE1cpu_crit _ criticalcooling-mapsmap0$0 )map1$1 )gpu_thermald/tripsgpu_alert0 ppassiveE2gpu_crit _ criticalcooling-mapsmap0$2 )tsadc@ff280000rockchip,rk3288-tsadc( %2HZztsadcapb_pclk tsadc-apbVinitdefaultsleepd384B3LbsokayyE/ethernet@ff290000rockchip,rk3288-gmac)macirqeth_wake_irq582fgc]Mzstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macB stmmacethok6inputVdefaultd789:;rgmii &'B@ ;<K0Tusb@ff500000 generic-ehciP 2zusbhost]=busb disabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T 2zotglhost]> busb2-phyokayusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X 2zotg lperipheralt@@ ]? busb2-phyokayusb@ff5c0000 generic-ehci\ 2zusbhost disabledi2c@ff650000rockchip,rk3288-i2ce <zi2c2LVdefaultd@okaysyr827@40silergy,syr827@vdd_cpu Pp&,B@WAEsyr828@41silergy,syr828Avdd_gpu PpWAhym8563@51haoyu,hym8563Qxin32kact8846@5aactive-semi,act8846ZVdefaultdBbzAAAAAACregulatorsREG1vcc_ddrREG2vcc_io2Z2ZEREG3vdd_logREG4vcc_20ECREG5 vccio_sd2Z2ZEREG6 vdd10_lcdB@B@REG7vcca_18w@w@REG8vcca_332Z2ZEWREG9vcc_lan2Z2ZE;REG10vdd_10B@B@REG11vcc_18w@w@EREG12 vcc18_lcdw@w@i2c@ff660000rockchip,rk3288-i2cf =zi2c2NVdefaultdDokaypwm@ff680000rockchip,rk3288-pwmhVdefaultdE2^zpwm disabledpwm@ff680010rockchip,rk3288-pwmhVdefaultdF2^zpwm disabledpwm@ff680020rockchip,rk3288-pwmh VdefaultdG2^zpwm disabledpwm@ff680030rockchip,rk3288-pwmh0VdefaultdH2^zpwm disabledbus_intmem@ff700000 mmio-srampMpsmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdsEpower-controller!rockchip,rk3288-power-controllerh E[pd_vio@9 2chgfdehilkj$IJKLMNOPQpd_hevc@11 2opRSpd_video@12 2Tpd_gpu@13 2UVreboot-modesyscon-reboot-modeRBRBRB !RBsyscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruv5-Hjk$:#gׄeрxhрxhEsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfdwE5edp-phyrockchip,rk3288-dp-phy2hz24mO disabledEkio-domains"rockchip,rk3288-io-voltage-domainokayZWgu;usbphyrockchip,rk3288-usb-phyokayusb-phy@320O 2]zphyclkE?usb-phy@334O42^zphyclkE=usb-phy@348OH2_zphyclkE>watchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt2p Ookaysound@ff88b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif zhclkmclk2TXtx 6VdefaultdY5 disabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s 5XXtxrxzi2s_hclki2s_clk2RVdefaultdZ disabledcypto-controller@ff8a0000rockchip,rk3288-crypto@ 0 2}zaclkhclksclkapb_pclk crypto-rstokayiommu@ff900800rockchip,iommu@ iep_mmu2 zaclkiface  disablediommu@ff914000rockchip,iommu @P isp_mmu2 zaclkiface  disabledrga@ff920000rockchip,rk3288-rga 2jzaclkhclksclk5[ ilm coreaxiahbvop@ff930000rockchip,rk3288-vop 2zaclk_vopdclk_vophclk_vop5[ def axiahbdclkC\okayportE endpoint@0J]Eoendpoint@1J^Elendpoint@2J_Efendpoint@3J`Eiiommu@ff930300rockchip,iommu  vopb_mmu2 zaclkiface5[  okayE\vop@ff940000rockchip,rk3288-vop 2zaclk_vopdclk_vophclk_vop5[  axiahbdclkCaokayportE endpoint@0JbEpendpoint@1JcEmendpoint@2JdEgendpoint@3JeEjiommu@ff940300rockchip,iommu  vopl_mmu2 zaclkiface5[  okayEamipi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi@ 2~d zrefpclk5[ 5 disabledportsportendpoint@0JfE_endpoint@1JgEdlvds@ff96c000rockchip,rk3288-lvds@2g zpclk_lvdsVlcdcdh5[ 5 disabledportsport@0endpoint@0JiE`endpoint@1JjEedp@ff970000rockchip,rk3288-dp@ b2iczdppclk]kbdpodp5 disabledportsport@0endpoint@0JlE^endpoint@1JmEchdmi@ff980000rockchip,rk3288-dw-hdmi5 g2hmnziahbisfrcec5[ okayZnportsportendpoint@0JoE]endpoint@1JpEbiommu@ff9a0800rockchip,iommu vpu_mmu2 zaclkiface  disablediommu@ff9c0440rockchip,iommu @@@ o hevc_mmu2 zaclkiface  disabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760$ jobmmugpu2fq5[  disabledgpu-opp-tableoperating-points-v2Eqopp@100000000z~opp@200000000z ~opp@300000000zB@opp@400000000zׄopp@500000000zeOopp@600000000z#Fqos@ffaa0000syscon EUqos@ffaa0080syscon EVqos@ffad0000syscon EJqos@ffad0100syscon EKqos@ffad0180syscon ELqos@ffad0400syscon EMqos@ffad0480syscon ENqos@ffad0500syscon EIqos@ffad0800syscon EOqos@ffad0880syscon EPqos@ffad0900syscon EQqos@ffae0000syscon ETqos@ffaf0000syscon ERqos@ffaf0080syscon ESinterrupt-controller@ffc01000 arm,gic-400@ @ `   Eefuse@ffb40000rockchip,rk3288-efuse 2q zpclk_efusecpu_leakage@17pinctrlrockchip,rk3288-pinctrl5Mgpio0@ff750000rockchip,gpio-banku Q2@Ezgpio1@ff780000rockchip,gpio-bankx R2Agpio2@ff790000rockchip,gpio-banky S2Bgpio3@ff7a0000rockchip,gpio-bankz T2Cgpio4@ff7b0000rockchip,gpio-bank{ U2DE<gpio5@ff7c0000rockchip,gpio-bank| V2Egpio6@ff7d0000rockchip,gpio-bank} W2Fgpio7@ff7e0000rockchip,gpio-bank~ X2GEygpio8@ff7f0000rockchip,gpio-bank Y2Hhdmihdmi-cec-c0rhdmi-cec-c7rhdmi-ddc rrpcfg-pull-upEspcfg-pull-downEtpcfg-pull-noneErpcfg-pull-none-12ma Eusleepglobal-pwroffrddrio-pwroffrddr0-retentionsddr1-retentionsedpedp-hpd ti2c0i2c0-xfer rrE@i2c1i2c1-xfer rrE&i2c2i2c2-xfer  r rEDi2c3i2c3-xfer rrE'i2c4i2c4-xfer rrE(i2c5i2c5-xfer rrE)i2s0i2s0-bus`rrrrrrEZlcdclcdc-ctl@rrrrEhsdmmcsdmmc-clkuE sdmmc-cmdvE sdmmc-cdsEsdmmc-bus1ssdmmc-bus4@vvvvEsdmmc-pwr rE|sdio0sdio0-bus1ssdio0-bus4@sssssdio0-cmdssdio0-clkrsdio0-cdssdio0-wpssdio0-pwrssdio0-bkpwrssdio0-intssdio1sdio1-bus1ssdio1-bus4@sssssdio1-cdssdio1-wpssdio1-bkpwrssdio1-intssdio1-cmdssdio1-clkrsdio1-pwr semmcemmc-clkrEemmc-cmdsEemmc-pwr sEemmc-bus1semmc-bus4@ssssemmc-bus8ssssssssEspi0spi0-clk sEspi0-cs0 sEspi0-txsEspi0-rxsEspi0-cs1sspi1spi1-clk sEspi1-cs0 sE!spi1-rxsE spi1-txsEspi2spi2-cs1sspi2-clksE"spi2-cs0sE%spi2-rxsE$spi2-tx sE#uart0uart0-xfer srE*uart0-ctssuart0-rtsruart1uart1-xfer s rE+uart1-cts suart1-rts ruart2uart2-xfer srE,uart3uart3-xfer srE-uart3-cts suart3-rts ruart4uart4-xfer srE.uart4-cts suart4-rts rtsadcotp-gpio rE3otp-out rE4pwm0pwm0-pinrEEpwm1pwm1-pinrEFpwm2pwm2-pinrEGpwm3pwm3-pinrEHgmacrgmii-pinsrrrruuuurrr uurrE7rmii-pinsrrrrrrrrrrphy-int sE:phy-pmebsE9phy-rstwE8spdifspdif-tx rEYpcfg-output-highEwpcfg-output-low#Expcfg-pull-up-drv-12ma Evact8846pmic-intspmic-sleepxpmic-vselxEBusb_hosthost-vbus-drvrE{chosen.serial2:115200n8memory@0memoryexternal-gmac-clock fixed-clocksY@ ext_gmacE6leds gpio-ledswork :y@miqi:green:userFtimerflash-regulatorregulator-fixed vcc_flashw@w@WEusb-host-regulatorregulator-fixed\ FzVdefaultd{ vcc_hostLK@LK@WAsdmmc-regulatorregulator-fixed Fy Vdefaultd|vcc_sd2Z2ZoWEvsys-regulatorregulator-fixedvcc_sysLK@LK@EA #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points#cooling-cellsclock-latencyclockscpu0-supplyphandleranges#dma-cellsarm,pl330-broken-no-flushpclock-namesstatusclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredportsmax-frequencyfifo-depthreset-namesbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaydisable-wppinctrl-namespinctrl-0vmmc-supplyvqmmc-supplynon-removable#io-channel-cellsvref-supplydmasdma-namesreg-shiftreg-io-widthpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesrockchip,grfassigned-clocksassigned-clock-parentsclock_in_outphy-supplyphy-modesnps,reset-active-lowsnps,reset-delays-ussnps,reset-gpiotx_delayrx_delayphysphy-namesdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizefcs,suspend-voltage-selectorregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onregulator-enable-ramp-delayregulator-ramp-delayvin-supplysystem-power-controllervp1-supplyvp2-supplyvp3-supplyvp4-supplyinl1-supplyinl2-supplyinl3-supply#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsaudio-supplyflash0-supplyflash1-supplygpio30-supplygpio1830-supplylcdc-supplysdcard-supplywifi-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointddc-i2c-busoperating-points-v2opp-hzopp-microvoltinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowstdout-pathgpioslabellinux,default-triggerenable-active-highstartup-delay-us