=8(h%amarula,vyasa-rk3288rockchip,rk3288&7Amarula Vyasa-RK3288aliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/dwmmc@ff0f0000k/dwmmc@ff0c0000q/dwmmc@ff0d0000w/dwmmc@ff0e0000}/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000arm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12`@p@ @OOa sB@ ~ ' 9  K 0 $@29Ecpu@501cpuarm,cortex-a12Ecpu@502cpuarm,cortex-a12Ecpu@503cpuarm,cortex-a12Eamba simple-busMdma-controller@ff250000arm,pl330arm,primecell%@T_2 zapb_pclkEdma-controller@ff600000arm,pl330arm,primecell`@T_2 zapb_pclk disableddma-controller@ffb20000arm,pl330arm,primecell@T_2 zapb_pclkEXreserved-memoryMdma-unusable@fe000000oscillator fixed-clockn6xin24mE timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer  H 2 a ztimerpclkdisplay-subsystemrockchip,display-subsystem dwmmc@ff0c0000rockchip,rk3288-dw-mshcр 2Drvzbiuciuciu-driveciu-sample  @resetokay (9KVdefaultd nzdwmmc@ff0d0000rockchip,rk3288-dw-mshcр 2Eswzbiuciuciu-driveciu-sample ! @reset disableddwmmc@ff0e0000rockchip,rk3288-dw-mshcр 2Ftxzbiuciuciu-driveciu-sample "@reset disableddwmmc@ff0f0000rockchip,rk3288-dw-mshcр 2Guyzbiuciuciu-driveciu-sample #@resetokay KVdefaultdnsaradc@ff100000rockchip,saradc $2I[zsaradcapb_pclkW saradc-apb disabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi2ARzspiclkapb_pclk  txrx ,Vdefaultd disabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi2BSzspiclkapb_pclk txrx -Vdefaultd disabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi2CTzspiclkapb_pclktxrx .Vdefaultd !"# disabledi2c@ff140000rockchip,rk3288-i2c >zi2c2MVdefaultd$ disabledi2c@ff150000rockchip,rk3288-i2c ?zi2c2OVdefaultd% disabledi2c@ff160000rockchip,rk3288-i2c @zi2c2PVdefaultd& disabledi2c@ff170000rockchip,rk3288-i2c Azi2c2QVdefaultd' disabledserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 72MUzbaudclkapb_pclkVdefaultd( disabledserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 82NVzbaudclkapb_pclkVdefaultd) disabledserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 92OWzbaudclkapb_pclkVdefaultd*okayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart :2PXzbaudclkapb_pclkVdefaultd+ disabledserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ;2QYzbaudclkapb_pclkVdefaultd, disabledthermal-zonesreserve_thermal-cpu_thermald-tripscpu_alert0p passiveE.cpu_alert1$ passiveE/cpu_crit_  criticalcooling-mapsmap0. map1/ gpu_thermald-tripsgpu_alert0p passiveE0gpu_crit_  criticalcooling-mapsmap00 tsadc@ff280000rockchip,rk3288-tsadc( %2HZztsadcapb_pclk tsadc-apbVinitdefaultsleepd1,261@VsokaymE-ethernet@ff290000rockchip,rk3288-gmac)macirqeth_wake_irq382fgc]Mzstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macB stmmacethokay4inputVdefaultd56789rgmii 'B@ /:?0Husb@ff500000 generic-ehciP 2zusbhostQ;Vusbokayusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T 2zotg`hostQ< Vusb2-phyokayVdefaultd=usb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X 2zotg`otghz@@ Q> Vusb2-phyokayusb@ff5c0000 generic-ehci\ 2zusbhost disabledi2c@ff650000rockchip,rk3288-i2ce <zi2c2LVdefaultd?okaypmic@1brockchip,rk808&@xin32krk808-clkout2VdefaultdABCCCCCCC'C4CAregulatorsDCDC_REG1Nvdd_arm] qupEregulator-state-memDCDC_REG2Nvdd_gpu] PuErregulator-state-memB@DCDC_REG3Nvcc_ddrregulator-state-memDCDC_REG4Nvcc_io]2Zu2ZEregulator-state-mem2ZLDO_REG1Nvcc_tp]2Zu2Zregulator-state-mem2ZLDO_REG2 Nvcc_codec]2Zu2Zregulator-state-memLDO_REG3Nvdd_10]B@uB@regulator-state-memB@LDO_REG4Nvcc_gps]w@uw@regulator-state-memw@LDO_REG5 Nvccio_sd]w@u2ZEregulator-state-mem2ZLDO_REG6 Nvcc10_lcd]B@uB@regulator-state-memw@LDO_REG7Nvcc_18]w@uw@EWregulator-state-memw@LDO_REG8 Nvcc18_lcd]w@uw@regulator-state-memw@SWITCH_REG1Nvcc_sd]2Zu2ZEregulator-state-memSWITCH_REG2Nvcc_lan]2Zu2ZE9regulator-state-memi2c@ff660000rockchip,rk3288-i2cf =zi2c2NVdefaultdDokayEnpwm@ff680000rockchip,rk3288-pwmhVdefaultdE2^zpwm disabledpwm@ff680010rockchip,rk3288-pwmhVdefaultdF2^zpwm disabledpwm@ff680020rockchip,rk3288-pwmh VdefaultdG2^zpwm disabledpwm@ff680030rockchip,rk3288-pwmh0VdefaultdH2^zpwm disabledbus_intmem@ff700000 mmio-srampMpsmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdsEpower-controller!rockchip,rk3288-power-controller h E[pd_vio@9 2chgfdehilkj$IJKLMNOPQpd_hevc@11 2opRSpd_video@12 2Tpd_gpu@13 2UVreboot-modesyscon-reboot-mode&-RB9RBGRB WRBsyscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruv3cHjk$p#gׄeрxhрxhEsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfdwE3edp-phyrockchip,rk3288-dp-phy2hz24m disabledEkio-domains"rockchip,rk3288-io-voltage-domainokayWW9Wusbphyrockchip,rk3288-usb-phyokayusb-phy@320 2]zphyclkE>usb-phy@33442^zphyclkE;usb-phy@348H2_zphyclkE<watchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt2p Ookaysound@ff88b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif  zhclkmclk2TXtx 6VdefaultdY3 disabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s  5XXtxrxzi2s_hclki2s_clk2RVdefaultdZ7 disabledcypto-controller@ff8a0000rockchip,rk3288-crypto@ 0 2}zaclkhclksclkapb_pclk crypto-rstokayiommu@ff900800rockchip,iommu@ iep_mmu2 zaclkifaceQ disablediommu@ff914000rockchip,iommu @P isp_mmu2 zaclkifaceQ^ disabledrga@ff920000rockchip,rk3288-rga 2jzaclkhclksclky[ ilm coreaxiahbvop@ff930000rockchip,rk3288-vop 2zaclk_vopdclk_vophclk_vopy[ def axiahbdclk\okayportE endpoint@0]Eoendpoint@1^Elendpoint@2_Efendpoint@3`Eiiommu@ff930300rockchip,iommu  vopb_mmu2 zaclkifacey[ QokayE\vop@ff940000rockchip,rk3288-vop 2zaclk_vopdclk_vophclk_vopy[  axiahbdclkaokayportE endpoint@0bEpendpoint@1cEmendpoint@2dEgendpoint@3eEjiommu@ff940300rockchip,iommu  vopl_mmu2 zaclkifacey[ QokayEamipi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi@ 2~d zrefpclky[ 3 disabledportsportendpoint@0fE_endpoint@1gEdlvds@ff96c000rockchip,rk3288-lvds@2g zpclk_lvdsVlcdcdhy[ 3 disabledportsport@0endpoint@0iE`endpoint@1jEedp@ff970000rockchip,rk3288-dp@ b2iczdppclkQkVdpodp3 disabledportsport@0endpoint@0lE^endpoint@1mEchdmi@ff980000rockchip,rk3288-dw-hdmi 3 g2hmnziahbisfrcecy[ okaynportsportendpoint@0oE]endpoint@1pEbiommu@ff9a0800rockchip,iommu vpu_mmu2 zaclkifaceQ disablediommu@ff9c0440rockchip,iommu @@@ o hevc_mmu2 zaclkifaceQ disabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760$ jobmmugpu2qy[ okayrgpu-opp-tableoperating-points-v2Eqopp@100000000~opp@200000000 ~opp@300000000B@opp@400000000ׄopp@500000000eOopp@600000000#Fqos@ffaa0000syscon EUqos@ffaa0080syscon EVqos@ffad0000syscon EJqos@ffad0100syscon EKqos@ffad0180syscon ELqos@ffad0400syscon EMqos@ffad0480syscon ENqos@ffad0500syscon EIqos@ffad0800syscon EOqos@ffad0880syscon EPqos@ffad0900syscon EQqos@ffae0000syscon ETqos@ffaf0000syscon ERqos@ffaf0080syscon ESinterrupt-controller@ffc01000 arm,gic-400@ @ `   Eefuse@ffb40000rockchip,rk3288-efuse 2q zpclk_efusecpu_leakage@17pinctrlrockchip,rk3288-pinctrl3Mgpio0@ff750000rockchip,gpio-banku Q2@E@gpio1@ff780000rockchip,gpio-bankx R2Agpio2@ff790000rockchip,gpio-banky S2Bgpio3@ff7a0000rockchip,gpio-bankz T2Cgpio4@ff7b0000rockchip,gpio-bank{ U2DE:gpio5@ff7c0000rockchip,gpio-bank| V2Egpio6@ff7d0000rockchip,gpio-bank} W2Fgpio7@ff7e0000rockchip,gpio-bank~ X2Ggpio8@ff7f0000rockchip,gpio-bank Y2HE{hdmihdmi-cec-c0!shdmi-cec-c7!shdmi-ddc !sspcfg-pull-up/Etpcfg-pull-down<Eupcfg-pull-noneKEspcfg-pull-none-12maKX Evsleepglobal-pwroff!sEBddrio-pwroff!sddr0-retention!tddr1-retention!tedpedp-hpd! ui2c0i2c0-xfer !ssE?i2c1i2c1-xfer !ssE$i2c2i2c2-xfer ! s sEDi2c3i2c3-xfer !ssE%i2c4i2c4-xfer !ssE&i2c5i2c5-xfer !ssE'i2s0i2s0-bus`!ssssssEZlcdclcdc-ctl@!ssssEhsdmmcsdmmc-clk!sE sdmmc-cmd!tE sdmmc-cd!tEsdmmc-bus1!tsdmmc-bus4@!ttttEsdio0sdio0-bus1!tsdio0-bus4@!ttttsdio0-cmd!tsdio0-clk!ssdio0-cd!tsdio0-wp!tsdio0-pwr!tsdio0-bkpwr!tsdio0-int!tsdio1sdio1-bus1!tsdio1-bus4@!ttttsdio1-cd!tsdio1-wp!tsdio1-bkpwr!tsdio1-int!tsdio1-cmd!tsdio1-clk!ssdio1-pwr! temmcemmc-clk!sEemmc-cmd!tEemmc-pwr! tEemmc-bus1!temmc-bus4@!ttttemmc-bus8!ttttttttEspi0spi0-clk! tEspi0-cs0! tEspi0-tx!tEspi0-rx!tEspi0-cs1!tspi1spi1-clk! tEspi1-cs0! tEspi1-rx!tEspi1-tx!tEspi2spi2-cs1!tspi2-clk!tE spi2-cs0!tE#spi2-rx!tE"spi2-tx! tE!uart0uart0-xfer !tsE(uart0-cts!tuart0-rts!suart1uart1-xfer !t sE)uart1-cts! tuart1-rts! suart2uart2-xfer !tsE*uart3uart3-xfer !tsE+uart3-cts! tuart3-rts! suart4uart4-xfer !tsE,uart4-cts! tuart4-rts! stsadcotp-gpio! sE1otp-out! sE2pwm0pwm0-pin!sEEpwm1pwm1-pin!sEFpwm2pwm2-pin!sEGpwm3pwm3-pin!sEHgmacrgmii-pins!ssssvvvvsss vvssE5rmii-pins!ssssssssssphy-int! tE8phy-pmeb!tE7phy-rst!wE6spdifspdif-tx! sEYpcfg-output-highgEwpmicpmic-int!tEAusb_hostphy-pwr-en! wE=usb2-pwr-en! sE|usb_otgotg-vbus-drv! sEychosens/serial@ff690000memorymemorydc12-vbatregulator-fixed Ndc12_vbat]uExvboot-3v3regulator-fixed Nvboot_3v3]2Zu2Zxvsys-regulatorregulator-fixedNvcc_sys]8u u8u xECvboot-5vregulator-fixed Nvboot_sv]LK@uLK@xv3g-3v3regulator-fixedNv3g_3v3]2Zu2Zxvsus-5vregulator-fixedNvsus_5v]LK@uLK@Ezvusb1-5vregulator-fixed Nvusb1_5v :@ Vdefaultdy]LK@uLK@zvusb2-5vregulator-fixed Nvusb2_5v :{ Vdefaultd|]LK@uLK@zexternal-gmac-clock fixed-clocksY@ ext_gmacE4 #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points#cooling-cellsclock-latencyclockscpu0-supplyphandleranges#dma-cellsarm,pl330-broken-no-flushpclock-namesstatusclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredportsmax-frequencyfifo-depthreset-namesbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaydisable-wppinctrl-namespinctrl-0vmmc-supplyvqmmc-supplynon-removable#io-channel-cellsdmasdma-namesreg-shiftreg-io-widthpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesrockchip,grfassigned-clocksassigned-clock-parentsclock_in_outphy-supplyphy-modesnps,reset-active-lowsnps,reset-delays-ussnps,reset-gpiotx_delayrx_delayphysphy-namesdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizerockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvolt#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsaudio-supplybb-supplydvp-supplyflash0-suuplyflash1-supplygpio30-supplygpio1830lcdc-supplysdcard-supplywifi-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointddc-i2c-busoperating-points-v2mali-supplyopp-hzopp-microvoltinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highstdout-pathvin-supplyenable-active-high