`8YH(Y*ad,medcom-widead,tamontennvidia,tegra20&!7Avionic Design Medcom-Wide boardchosen=serial0:115200n8aliasesI/i2c@7000d000/tps6586x@34N/rtc@7000e000S/serial@70006300memory[memoryg iram@40000000 mmio-sramg@ k@vde@400grw host1x@50000000!nvidia,tegra20-host1xsimple-busgP@AChost1x kTTmpe@54040000nvidia,tegra20-mpegT D<<mpevi@54080000nvidia,tegra20-vigT Edviepp@540c0000nvidia,tegra20-eppgT  Feppisp@54100000nvidia,tegra20-ispgT Gispgr2d@54140000nvidia,tegra20-gr2dgT H2dgr3d@54180000nvidia,tegra20-gr3dgT3ddc@54200000nvidia,tegra20-dcgT  Iy dcparentdcrgbokaydc@54240000nvidia,tegra20-dcgT$ Jy dcparentdcrgb disabledhdmi@54280000nvidia,tegra20-hdmigT( K3u hdmiparent3hdmi disabled otvo@542c0000nvidia,tegra20-tvogT, Lf disableddsi@54300000nvidia,tegra20-dsigT000dsi disabledtimer@50040600arm,cortex-a9-twd-timer&gP   interrupt-controller@50041000arm,cortex-a9-gicgPP &wcache-controller@50043000arm,pl310-cachegP0 / @P^interrupt-controller@60004000nvidia,tegra20-ictlr g`@`AP`BP`CP &wtimer@60005000nvidia,tegra20-timerg`P`0)*clock@60006000nvidia,tegra20-carg``jwwflow-controller@60007000nvidia,tegra20-flowctrlg`pdma@6000a000nvidia,tegra20-apbdmag`hijklmnopqrstuvw""dmaw ahb@6000c000nvidia,tegra20-ahbg`gpio@6000d000nvidia,tegra20-gpiog`T !"#7WY wvde@6001a000nvidia,tegra20-vdeHg`````````*sxebsevmbeppemcetfeppbvdmaframeid $   sync-tokenbsevsxe==apbmisc@70000800nvidia,tegra20-apbmiscgpdppinmux@70000014nvidia,tegra20-pinmux gpp pphdefault pinmuxw ataataideatb atbgmagmesdio4atcatcnandatd#atdategmbgmdgpuspiaspibspicgmicdev1cdev1 plla_outcdev2cdev2 pllp_out4crtpcrtpcrtcsuscsusvi_sensor_clkdap1dap1dap1dap2dap2dap2dap3dap3dap3dap4dap4dap4dtadtadtdsdio2dtb dtbdtcdtersvd1dtfdtfi2c3gmcgmcuartdgpu7gpu7rtckgpvgpvslxaslxkpciehdinthdinthdmii2cpi2cpi2cpirrx irrxirtxuartakbcakbcakbcbkbcckbcdkbcekbcfkbclcsnlcsnld0ld1ld2ld3ld4ld5ld6ld7ld8ld9ld10ld11ld12ld13ld14ld15ld16ld17ldcldilhp0lhp1lhp2lhslm0lm1lpplpw0lpw1lpw2lsc0lsc1lscklsdalsdilspilvp0lvp1lvs displayaowcowcspdispdouacrsvd2pmcpmcpwr_onrmrmi2c1sdb sdbsdcsddpwmsdio1sdio1sdio1slxc slxcslxdspdifspidspidspiespifspi1spig spigspih spi2_altuaa uaauabudaulpiuaduadirdaucaucaucbuartcconf_atajataatbatcatdatecdev1cdev2dap1dtbgmagmbgmcgmdgmegpu7gpvi2cpptarmslxaslxkspiaspibuac conf_ck32-ck32ddrcpmcapmcbpmccpmcdpmcexm2cxm2dconf_csuscsusspidspif conf_crtpGcrtpdap2dap3dap4dtcdtedtfgpusdio1slxcslxdspdispdospiguda conf_ddc.ddcdtadtdkbcakbcbkbcckbcdkbcekbcfsdc conf_hdint9hdintlcsnldclm1lpw1lsc1lscklsdalsdilvp0owcsdb conf_irrx1irrxirtxsddspicspiespihuaauabuaducaucb conf_lclclsconf_ld0ld0ld1ld2ld3ld4ld5ld6ld7ld8ld9ld10ld11ld12ld13ld14ld15ld16ld17ldilhp0lhp1lhp2lhslm0lpplpw0lpw2lsc0lspilvp1lvspmc conf_ld17_0ld17_0ld19_18ld21_20ld23_22pinmux_i2cmux_ddcwddcddci2c2ptaptarsvd4pinmux_i2cmux_ptawddcddcrsvd4ptaptai2c2pinmux_i2cmux_idlewddcddcrsvd4ptaptarsvd4das@70000c00nvidia,tegra20-dasgp ac97@70002000nvidia,tegra20-ac97gp  Qac97 rxtx disabledi2s@70002800nvidia,tegra20-i2sgp(    i2s  rxtxokaywi2s@70002a00nvidia,tegra20-i2sgp* i2s  rxtx disabledserial@70006000nvidia,tegra20-uartgp`@) $serial  rxtx disabledserial@70006040nvidia,tegra20-uartgp`@@) %`serial rxtx disabledserial@70006200nvidia,tegra20-uartgpb) .77serial rxtx disabledserial@70006300nvidia,tegra20-uartgpc) ZAAserial  rxtxokayserial@70006400nvidia,tegra20-uartgpd) [BBserial  rxtx disabledgmi@70009000nvidia,tegra20-gmigpk*gmi*gmi disabledpwm@7000a000nvidia,tegra20-pwmgp3pwmokaywrtc@7000e000nvidia,tegra20-rtcgp i2c@7000c000nvidia,tegra20-i2cgp & |div-clkfast-clk i2c  rxtxokay>wm8903@1a wlf,wm8903g&NYdfw spi@7000c380nvidia,tegra20-sflashgpÀ '++spi rxtx disabledi2c@7000c400nvidia,tegra20-i2cgp T6|div-clkfast-clk6i2c  rxtxokay>wi2c@7000c500nvidia,tegra20-i2cgp \C|div-clkfast-clkCi2c  rxtx disabledi2c@7000d000nvidia,tegra20-i2c-dvcgp 5/|div-clkfast-clk/i2c  rxtxokay>tps6586x@34 ti,tps6586xg4 Vo    wregulatorssysvdd_sys w sm0vdd_sys_sm0,vdd_core4OLO sm1vdd_sys_sm1,vdd_cpu4B@LB@ sm2vdd_sys_sm2,vin_ldo*48u L8u  wldo0vdd_ldo0,vddio_pex_clk42ZL2Zwldo1vdd_ldo1,avdd_pll*4L ldo2vdd_ldo2,vdd_rtc4OLOldo3vdd_ldo3,avdd_usb*42ZL2Z ldo4vdd_ldo4,avdd_osc,vddio_sys4w@Lw@ ldo5vdd_ldo5,vcore_mmc4+|L+|ldo6vdd_ldo6,avdd_vdac4+|L+|ldo7vdd_ldo7,avdd_hdmi42ZL2Zwldo8vdd_ldo8,avdd_hdmi_pll4w@Lw@wldo9vdd_ldo9,vdd_ddr_rx,avdd_cam4+|L+| ldo_rtc vdd_rtc_out42ZL2Z temperature-sensor@4c onnn,nct1008gLspi@7000d400nvidia,tegra20-slinkgp ;))spi  rxtx disabledspi@7000d600nvidia,tegra20-slinkgp R,,spi  rxtx disabledspi@7000d800nvidia,tegra20-slinkgp S..spi  rxtx disabledspi@7000da00nvidia,tegra20-slinkgp ]DDspi  rxtx disabledkbc@7000e200nvidia,tegra20-kbcgp U$$kbc disabledpmc@7000e400nvidia,tegra20-pmcgp npclkclk32k_ind|#memory-controller@7000f000nvidia,tegra20-mcgp$p< Miommu@7000f024nvidia,tegra20-gartgp$Xmemory-controller@7000f400nvidia,tegra20-emcgpfuse@7000f800nvidia,tegra20-efusegp'fuse'fusepcie@80003000nvidia,tegra20-pcie[pcig08 padsaficsbc intrmsi (b6xkFHvpexafipll_eFHJpexafipcie_x disabled@APdupci@1,0[pcig6 disabledkpci@2,0[pcig6 disabledkusb@c5000000nvidia,tegra20-ehciusb-ehcig@ utmiusb disabledusb-phy@c5000000nvidia,tegra20-usb-phyg@@utmi jregpll_utimerutmi-padsusbutmi-pads  $9O au disabledwusb@c5004000nvidia,tegra20-ehciusb-ehcig@@ ulpi::usb disabledusb-phy@c5004000nvidia,tegra20-usb-phyg@@ulpi:]regpll_uulpi-link:usbutmi-pads disabledwusb@c5008000nvidia,tegra20-ehciusb-ehcig@ autmi;;usbokayusb-phy@c5008000nvidia,tegra20-usb-phyg@@utmi ;jregpll_utimerutmi-pads;usbutmi-pads  $9O auokaywsdhci@c8000000nvidia,tegra20-sdhcig sdhci disabledsdhci@c8000200nvidia,tegra20-sdhcig   sdhci disabledsdhci@c8000400nvidia,tegra20-sdhcig EEsdhci disabledsdhci@c8000600nvidia,tegra20-sdhcig sdhciokay : ;cpuscpu@0[cpuarm,cortex-a9gcpu@1[cpuarm,cortex-a9gpmuarm,cortex-a9-pmu89i2cmuxi2c-mux-pinctrl ddcptaidlei2c@0gwi2c@1gclocks simple-busclock@0 fixed-clockgj>wregulators simple-busregulator@1regulator-fixedg vdd_1v054L wregulator@100regulator-fixedgdvcc_24v4n6Ln6 wregulator@101regulator-fixedgevdd_5v04LK@LLK@ w regulator@102regulator-fixedgfvdd_3v342ZL2Z wregulator@103regulator-fixedggvdd_1v84w@Lw@ wbacklightpwm-backlight LK@  @wpanel!innolux,n156bge-l21simple-panel0 = Jwsound<ad,tegra-audio-wm8903-medcom-widenvidia,tegra-audio-wm8903TAvionic Design Medcom-Wide{aHeadphone JackHPOUTRHeadphone JackHPOUTLInt SpkROPInt SpkRONInt SpkLOPInt SpkLONMic JackMICBIASIN1LMic Jackv    pq^pll_apll_a_out0mclk #address-cells#size-cellscompatibleinterrupt-parentmodelstdout-pathrtc0rtc1serial0device_typeregrangespoolphandleinterruptsclocksresetsreset-namesclock-namesnvidia,headstatusnvidia,panelvdd-supplypll-supplynvidia,ddc-i2c-busnvidia,hpd-gpiointerrupt-controller#interrupt-cellsarm,data-latencyarm,tag-latencycache-unifiedcache-level#clock-cells#reset-cells#dma-cells#gpio-cellsgpio-controllerreg-namesiraminterrupt-namespinctrl-namespinctrl-0nvidia,pinsnvidia,functionnvidia,pullnvidia,tristatedmasdma-namesreg-shift#pwm-cellsclock-frequencymicdet-cfgmicdet-delaygpio-cfgti,system-power-controllersys-supplyvin-sm0-supplyvin-sm1-supplyvin-sm2-supplyvinldo01-supplyvinldo23-supplyvinldo4-supplyvinldo678-supplyvinldo9-supplyregulator-nameregulator-always-onregulator-min-microvoltregulator-max-microvoltnvidia,invert-interruptnvidia,suspend-modenvidia,cpu-pwr-good-timenvidia,cpu-pwr-off-timenvidia,core-pwr-good-timenvidia,core-pwr-off-timenvidia,sys-clock-req-active-highinterrupt-map-maskinterrupt-mapbus-rangeavdd-pex-supplyavdd-pex-pll-supplyavdd-plle-supplyvddio-pex-clk-supplyassigned-addressesnvidia,num-lanesphy_typenvidia,has-legacy-modenvidia,needs-double-resetnvidia,phynvidia,hssync-start-delaynvidia,idle-wait-delaynvidia,elastic-limitnvidia,term-range-adjnvidia,xcvr-setupnvidia,xcvr-lsfslewnvidia,xcvr-lsrslewnvidia,has-utmi-pad-registerscd-gpioswp-gpiosbus-widthi2c-parentpinctrl-1pinctrl-2enable-active-highvin-supplypwmsbrightness-levelsdefault-brightness-levelpower-supplyenable-gpiosbacklightnvidia,modelnvidia,audio-routingnvidia,i2s-controllernvidia,audio-codecnvidia,spkr-en-gpiosnvidia,hp-det-gpios