8(\ ,NXP i.MX7ULP EVK2fsl,imx7ulp-evkfsl,imx7ulpaliases=/bus@40800000/gpio@40ae0000C/bus@40800000/gpio@40af0000I/bus@40800000/gpio@40b00000O/bus@40800000/gpio@40b10000U/bus@40800000/i2c@40a40000Z/bus@40800000/i2c@40a50000_/bus@40000000/mmc@40370000d/bus@40000000/mmc@40380000i/bus@40000000/serial@402d0000q/bus@40000000/serial@402e0000y/bus@40800000/serial@40a60000/bus@40800000/serial@40a70000cpus cpu@02arm,cortex-a7cpuinterrupt-controller@400210002arm,cortex-a7-gic@@ clock-rosc 2fixed-clockroscclock-sosc 2fixed-clockn6sosc clock-sirc 2fixed-clock$sirc clock-firc 2fixed-clocklfirc clock-upll 2fixed-clock8upll clock-mpll 2fixed-clock8mpll bus@40000000 2simple-bus @serial@402d00002fsl,imx7ulp-lpuart@-  ipg,)Cn6Xokay_defaultmserial@402e00002fsl,imx7ulp-lpuart@.  ipg,Cl Xdisabledtpm@402600002fsl,imx7ulp-tpm@&  %ipgpermmc@40370000#2fsl,imx7ulp-usdhcfsl,imx6sx-usdhc@7 * %$ ipgahbper,$wXokay_defaultm  mmc@40380000#2fsl,imx7ulp-usdhcfsl,imx6sx-usdhc@8 + %$ ipgahbper,$w Xdisabledclock-controller@403e00002fsl,imx7ulp-scg1@>  roscsoscsircfircupllmpllclock-controller@403f00002fsl,imx7ulp-pcc2@?` %$ )'*+rnic1_bus_clknic1_clkddr_clkapll_pfd2apll_pfd1apll_pfd0upllsosc_bus_clkmpllfirc_bus_clkroscspll_bus_clk,)smc1@404100002fsl,imx7ulp-smc1@Aclock-controller@40b300002fsl,imx7ulp-pcc3@` %$ )'*+rnic1_bus_clknic1_clkddr_clkapll_pfd2apll_pfd1apll_pfd0upllsosc_bus_clkmpllfirc_bus_clkroscspll_bus_clkbus@40800000 2simple-bus @i2c@40a400002fsl,imx7ulp-lpi2c@ $ ipg,Cl Xdisabledi2c@40a500002fsl,imx7ulp-lpi2c@ % ipg,Cl Xdisabledserial@40a600002fsl,imx7ulp-lpuart@  ipg,Cl Xdisabledserial@40a700002fsl,imx7ulp-lpuart@ ! ipg,Cl Xdisabledpinctrl@40ac00002fsl,imx7ulp-iomuxc1@lpuart4grp( HLusdhc0grpC@CCCC(usdhc0-gpio-rst-grpgpio@40ae0000 2fsl,imx7ulp-gpiofsl,vf610-gpio@@@ 0   gpioport gpio@40af0000 2fsl,imx7ulp-gpiofsl,vf610-gpio@@@@ 1   gpioport gpio@40b00000 2fsl,imx7ulp-gpiofsl,vf610-gpio@@@ 2   gpioport@ gpio@40b10000 2fsl,imx7ulp-gpiofsl,vf610-gpio@@@ 3   gpioport` chosen/bus@40000000/serial@402d0000memory@60000000memory`@regulator-vsd-3v32regulator-fixedVSD_3V32Z,2Z_defaultm DI interrupt-parent#address-cells#size-cellsmodelcompatiblegpio0gpio1gpio2gpio3i2c0i2c1mmc0mmc1serial0serial1serial2serial3device_typereg#interrupt-cellsinterrupt-controllerphandleclock-frequencyclock-output-names#clock-cellsrangesinterruptsclocksclock-namesassigned-clocksassigned-clock-parentsassigned-clock-ratesstatuspinctrl-namespinctrl-0bus-widthfsl,tuning-start-tapfsl,tuning-stepcd-gpiosvmmc-supplyfsl,pinsbias-pull-upgpio-controller#gpio-cellsgpio-rangesstdout-pathregulator-nameregulator-min-microvoltregulator-max-microvoltgpioenable-active-high