Ð þíUÛ8P|(_PD',mundoreader,bq-curie2rockchip,rk3066a 7bq Curie 2aliases=/ethernet@10204000G/i2c@2002d000L/i2c@2002f000Q/i2c@20056000V/i2c@2005a000[/i2c@2005e000`/dwmmc@1021c000f/dwmmc@10214000l/dwmmc@10218000r/serial@10124000z/serial@10126000‚/serial@20064000Š/serial@20068000’/spi@20070000—/spi@20074000amba ,simple-busœdma-controller@20018000,arm,pl330arm,primecell£ €@§²½ØÀ ßapb_pclkëdma-controller@2001c000,arm,pl330arm,primecell£ À@§²½ØÀ ßapb_pclk ódisableddma-controller@20078000,arm,pl330arm,primecell£ €@§²½ØÁ ßapb_pclkë oscillator ,fixed-clockún6 xin24mgpu@10090000",rockchip,rk3066-maliarm,mali-400£ ØÅÅ ßcorebus*Å:õáOx ódisabledx§5Vgpgpmmupp0ppmmu0pp1ppmmu1pp2ppmmu2pp3ppmmu3fl2-cache-controller@10138000,arm,pl310-cache£€t‚ë0scu@1013c000,arm,cortex-a9-scu£Àglobal-timer@1013c200,arm,cortex-a9-global-timer£  § Ølocal-timer@1013c600,arm,cortex-a9-twd-timer£Æ  § Øinterrupt-controller@1013d000,arm,cortex-a9-gicŽ££ÐÁëserial@10124000&,rockchip,rk3066-uartsnps,dw-apb-uart£@ §"´¾ßbaudclkapb_pclkØ@LóokayËÐtxrxÚdefaultèserial@10126000&,rockchip,rk3066-uartsnps,dw-apb-uart£` §#´¾ßbaudclkapb_pclkØAMóokayËÐtxrxÚdefaultèqos@1012d000,syscon£Ð ëqos@1012e000,syscon£à ëqos@1012f000,syscon£ð ëqos@1012f080,syscon£ð€ ëqos@1012f100,syscon£ñ ëqos@1012f180,syscon£ñ€ ëqos@1012f200,syscon£ò ëqos@1012f280,syscon£ò€ ëusb@10180000,rockchip,rk3066-usbsnps,dwc2£ §ØÃßotgòotgú €€@@ * /usb2-phy ódisabledusb@101c0000 ,snps,dwc2£ §ØÉßotgòhost* /usb2-phy ódisabledethernet@10204000,rockchip,rk3066-emac£ @< §9 ØÄD ßhclkmacrefFdPrmii ódisableddwmmc@10214000,rockchip,rk2928-dw-mshc£!@ §ØÀHßbiuciuË Ðrx-txYOQdresetóokayúúð€púð€Údefaultè ~Š”¦·dwmmc@10218000,rockchip,rk2928-dw-mshc£!€ §ØÁIßbiuciuË Ðrx-txYORdresetóokayÚdefault 芷dwmmc@1021c000,rockchip,rk2928-dw-mshc£!À §ØÂJßbiuciuË Ðrx-txYOSdreset ódisabledpmu@20004000&,rockchip,rk3066-pmusysconsimple-mfd£ @reboot-mode,syscon-reboot-modeÐ@×RBÃãRBÃñRBà RBÃpower-controller!,rockchip,rk3066-power-controller ëpd_vio@7£€ØÃľ¿ÍÎPÇÖOÊÐÈÑÉÒ!pd_video@6£ ØÎÍØ×!pd_gpu@8£ØÅ!grf@20008000,syscon£ €ë i2c@2002d000,rockchip,rk3066-i2c£ Ð §(9 ßi2cØP ódisabledÚdefaultèi2c@2002f000,rockchip,rk3066-i2c£ ð §)9 ØQßi2cóokayÚdefaultèú€tps@2d£-§(4 ,ti,tps65910regulatorsregulator@0@vcc_rtcO£cvrtcregulator@1@vcc_ioO£cvioëregulator@2@vdd_armx 'Àã`¨O£cvdd1ë1regulator@3@vcc_ddrx 'Àã`¨O£cvdd2regulator@5 @vcc18_cifO£cvdig1regulator@6@vdd_11O£cvdig2regulator@7@vcc_25O£cvpllregulator@8@vcc_18O£cvdacregulator@9 @vcc25_hdmiO£ cvaux1regulator@10@vcca_33O£ cvaux2regulator@11@vcc_tpO£ cvaux33regulator@12 @vcc28_cifO£ cvmmcregulator@4£cvdd3regulator@13£ cvbbpwm@20030000,rockchip,rk2928-pwm£ ºØF ódisabledÚdefaultèpwm@20030010,rockchip,rk2928-pwm£ ºØF ódisabledÚdefaultè watchdog@2004c000 ,rockchip,rk3066-wdtsnps,dw-wdt£ ÀØK §3óokaypwm@20050020,rockchip,rk2928-pwm£  ºØG ódisabledÚdefaultè!pwm@20050030,rockchip,rk2928-pwm£ 0ºØGóokayÚdefaultè"ë7i2c@20056000,rockchip,rk3066-i2c£ ` §*9 ØRßi2c ódisabledÚdefaultè#i2c@2005a000,rockchip,rk3066-i2c£   §+9 ØSßi2c ódisabledÚdefaultè$i2c@2005e000,rockchip,rk3066-i2c£ à §49 ØTßi2c ódisabledÚdefaultè%serial@20064000&,rockchip,rk3066-uartsnps,dw-apb-uart£ @ §$´¾ßbaudclkapb_pclkØBNóokayË  ÐtxrxÚdefaultè&serial@20068000&,rockchip,rk3066-uartsnps,dw-apb-uart£ € §%´¾ßbaudclkapb_pclkØCOóokayË  ÐtxrxÚdefaultè'saradc@2006c000,rockchip,saradc£ À §ÅØGJßsaradcapb_pclkOW dsaradc-apb ódisabledspi@20070000,rockchip,rk3066-spiØEHßspiclkapb_pclk §&£ Ë Ðtxrx ódisabledÚdefaultè()*+spi@20074000,rockchip,rk3066-spiØFIßspiclkapb_pclk §'£ @Ë Ðtxrx ódisabledÚdefaultè,-./cpus×rockchip,rk3066-smpcpu@0åcpu,arm,cortex-a9ñ0£8›@Ö O€íØa€*ˆ s€*ˆ 'ÀÈà°ÀÈàÂÀg8œ@Ø!1cpu@1åcpu,arm,cortex-a9ñ0£sram@10080000 ,mmio-sram£ œsmp-sram@0,rockchip,rk3066-smp-sram£Pi2s@10118000,rockchip,rk3066-i2s£€  §Údefaultè2ËÐtxrxßi2s_hclki2s_clkØÆK-Hb ódisabledi2s@1011a000,rockchip,rk3066-i2s£   § Údefaultè3ËÐtxrxßi2s_hclki2s_clkØÇL-Hb ódisabledi2s@1011c000,rockchip,rk3066-i2s£À  §Údefaultè4Ë  Ðtxrxßi2s_hclki2s_clkØÈM-Hb ódisabledclock-controller@20000000,rockchip,rk3066a-cru£ 9  s@*ËÔ^ÌÕ_ :ׄ#g¸€á£ðÑ€xhÀá£ðÑ€xhÀëtimer@2000e000,snps,dw-apb-timer-osc£ à §.ØVD ßtimerpclkefuse@20010000,rockchip,rk3066a-efuse£ @Ø[ ßpclk_efusecpu_leakage@17£timer@20038000,snps,dw-apb-timer-osc£ € §,ØTB ßtimerpclktimer@2003a000,snps,dw-apb-timer-osc£   §-ØUC ßtimerpclktsadc@20060000,rockchip,rk3066-tsadc£ Ø]]ßsaradcapb_pclk §ÅO\ dsaradc-apb ódisabledphy1,rockchip,rk3066a-usb-phyrockchip,rk3288-usb-phy9  ódisabledusb-phy@17c€£|ØQßphyclk ëusb-phy@188€£ˆØRßphyclk ëpinctrl,rockchip,rk3066a-pinctrl9 œgpio0@20034000,rockchip,gpio-bank£ @ §6ØU‹›Ž£gpio1@2003c000,rockchip,gpio-bank£ À §7ØV‹›Ž£gpio2@2003e000,rockchip,gpio-bank£ à §8ØW‹›Ž£gpio3@20080000,rockchip,gpio-bank£  §9ØX‹›Ž£ë8gpio4@20084000,rockchip,gpio-bank£ @ §:ØY‹›Ž£ë9gpio6@2000a000,rockchip,gpio-bank£   §<ØZ‹›Ž£ëpcfg_pull_default§ë6pcfg_pull_none½ë5emacemac-xfer€Ê55555555emac-mdio Ê55emmcemmc-clkÊ6emmc-cmdÊ 6emmc-rstÊ 6i2c0i2c0-xfer Ê55ëi2c1i2c1-xfer Ê55ëi2c2i2c2-xfer Ê55ë#i2c3i2c3-xfer Ê55ë$i2c4i2c4-xfer Ê55ë%pwm0pwm0-outÊ5ëpwm1pwm1-outÊ5ë pwm2pwm2-outÊ5ë!pwm3pwm3-outÊ5ë"spi0spi0-clkÊ6ë(spi0-cs0Ê6ë+spi0-txÊ6ë)spi0-rxÊ6ë*spi0-cs1Ê6spi1spi1-clkÊ6ë,spi1-cs0Ê6ë/spi1-rxÊ6ë.spi1-txÊ6ë-spi1-cs1Ê6uart0uart0-xfer Ê66ëuart0-ctsÊ6uart0-rtsÊ6uart1uart1-xfer Ê66ëuart1-ctsÊ6uart1-rtsÊ6uart2uart2-xfer Ê6 6ë&uart3uart3-xfer Ê66ë'uart3-ctsÊ6uart3-rtsÊ6sd0sd0-clkÊ6ë sd0-cmdÊ 6ë sd0-cdÊ6ë sd0-wpÊ6sd0-bus-width1Ê 6sd0-bus-width4@Ê 6 6 6 6ësd1sd1-clkÊ6ësd1-cmdÊ6ësd1-cdÊ6sd1-wpÊ6sd1-bus-width1Ê6sd1-bus-width4@Ê6666ëi2s0i2s0-busÊ66 6 6 6 6 666ë2i2s1i2s1-bus`Ê666666ë3i2s2i2s2-bus`Ê666666ë4memory@60000000åmemory£`@vdd-log,pwm-regulator Ø7è@vdd_logxO€O€OÝB@dO€*óokayfixed-regulator,regulator-fixed @sdmmc-supplyx-ÆÀ-ÆÀ ë8ð† ëgpio-keys ,gpio-keys power t(GPIO Key Power.?Mdvolume-down 9r(GPIO Key Vol-.Md #address-cells#size-cellsinterrupt-parentcompatiblemodelethernet0i2c0i2c1i2c2i2c3i2c4mshc0mshc1mshc2serial0serial1serial2serial3spi0spi1rangesreginterrupts#dma-cellsarm,pl330-broken-no-flushpclocksclock-namesphandlestatusclock-frequency#clock-cellsclock-output-namesassigned-clocksassigned-clock-ratesresetsinterrupt-namespower-domainscache-unifiedcache-levelinterrupt-controller#interrupt-cellsreg-shiftreg-io-widthdmasdma-namespinctrl-namespinctrl-0dr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephysphy-namesrockchip,grfmax-speedphy-modefifo-depthreset-namesmax-frequencyvmmc-supplybus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpnon-removableoffsetmode-normalmode-recoverymode-bootloadermode-loader#power-domain-cellspm_qosvcc5-supplyvcc6-supplyregulator-nameregulator-always-onregulator-compatibleregulator-min-microvoltregulator-max-microvoltregulator-boot-on#pwm-cells#io-channel-cellsenable-methoddevice_typenext-level-cacheoperating-pointsclock-latencycpu0-supplyrockchip,playback-channelsrockchip,capture-channels#sound-dai-cells#reset-cells#phy-cellsgpio-controller#gpio-cellsbias-pull-pin-defaultbias-disablerockchip,pinspwmsvoltage-tablegpiostartup-delay-usvin-supplyautorepeatgpioslinux,codelabellinux,input-typewakeup-sourcedebounce-interval