Ð þíZØ8Tl(lT4.,rockchip,px3-evbrockchip,px3rockchip,rk31887Rockchip PX3-EVBaliases=/ethernet@10204000G/i2c@2002d000L/i2c@2002f000Q/i2c@20056000V/i2c@2005a000[/i2c@2005e000`/dwmmc@1021c000f/dwmmc@10214000l/dwmmc@10218000r/serial@10124000z/serial@10126000‚/serial@20064000Š/serial@20068000’/spi@20070000—/spi@20074000amba ,simple-busœdma-controller@20018000,arm,pl330arm,primecell£ €@§²½ØÀ ßapb_pclkë6dma-controller@2001c000,arm,pl330arm,primecell£ À@§²½ØÀ ßapb_pclk ódisableddma-controller@20078000,arm,pl330arm,primecell£ €@§²½ØÁ ßapb_pclkë oscillator ,fixed-clockún6 xin24mgpu@10090000",rockchip,rk3188-maliarm,mali-400£ ØÅÅ ßcorebus*Å:õáOx ódisabledx§ 5Vgpgpmmupp0ppmmu0pp1ppmmu1pp2ppmmu2pp3ppmmu3fl2-cache-controller@10138000,arm,pl310-cache£€t‚ë0scu@1013c000,arm,cortex-a9-scu£Àglobal-timer@1013c200,arm,cortex-a9-global-timer£  § Ø ódisabledlocal-timer@1013c600,arm,cortex-a9-twd-timer£Æ  § Øinterrupt-controller@1013d000,arm,cortex-a9-gicŽ££ÐÁëserial@10124000&,rockchip,rk3188-uartsnps,dw-apb-uart£@ §"´¾ßbaudclkapb_pclkØ@LóokayËdefaultÙserial@10126000&,rockchip,rk3188-uartsnps,dw-apb-uart£` §#´¾ßbaudclkapb_pclkØAMóokayËdefaultÙqos@1012d000,syscon£Ð ëqos@1012e000,syscon£à ëqos@1012f000,syscon£ð ëqos@1012f080,syscon£ð€ ëqos@1012f100,syscon£ñ ëqos@1012f180,syscon£ñ€ ëqos@1012f200,syscon£ò qos@1012f280,syscon£ò€ ëusb@10180000,rockchip,rk3066-usbsnps,dwc2£ §ØÃßotgãotgëý €€@@   usb2-phyóokayusb@101c0000 ,snps,dwc2£ §ØÉßotgãhost  usb2-phyóokayethernet@10204000,rockchip,rk3188-emac£ @< §*ØÄD ßhclkmacref7dArmii ódisableddwmmc@10214000,rockchip,rk2928-dw-mshc£!@ §ØÀHßbiuciuJ Orx-txYOQdresetóokayËdefaultÙ p|†˜©dwmmc@10218000,rockchip,rk2928-dw-mshc£!€ §ØÁIßbiuciuJ Orx-txYORdreset ódisableddwmmc@1021c000,rockchip,rk2928-dw-mshc£!À §ØÂJßbiuciuJ Orx-txYOSdresetóokay|†©´Ëdefault Ùpmu@20004000&,rockchip,rk3066-pmusysconsimple-mfd£ @ë8reboot-mode,syscon-reboot-modeÂ@ÉRBÃÕRBÃãRBà óRBÃpower-controller!,rockchip,rk3188-power-controllerÿëpd_vio@7£hØÃľ¿ÍÎOÊÐÈÑÉÒpd_video@6£ ØÎÍØ×pd_gpu@8£ØÅgrf@20008000,syscon£ €ëi2c@2002d000,rockchip,rk3188-i2c£ Ð §(*ßi2cØPóokayËdefaultÙaccelerometer@18 ,bosch,bma250£§i2c@2002f000,rockchip,rk3188-i2c£ ð §)*ØQßi2cóokayËdefaultÙú€pmic@1c,rockchip,rk818£§ ; xin32krk808-clkout2IUamy…‘regulatorsDCDC_REG1©½Ï q°ç™pÿvdd_armë2regulator-state-memDCDC_REG2©½Ï øPçÐÿvdd_gpuregulator-state-mem'?B@DCDC_REG3©½ÿvcc_ddrregulator-state-mem'DCDC_REG4©½Ï2Z ç2Z ÿvcc_ioëregulator-state-mem'?2Z LDO_REG1Ï2Z ç2Z ÿvcc_cifLDO_REG2©½Ï2Z ç2Z  ÿvcc_jetta33LDO_REG3©½ÏB@çB@ÿvdd_10regulator-state-mem'?B@LDO_REG4Ïw@çw@ÿlvds_12LDO_REG5Ïw@ç2Z ÿlvds_25LDO_REG6ÏB@çB@ÿcif_18LDO_REG7Ïw@ç2Z ÿvcc_sdëregulator-state-mem'?2Z LDO_REG8Ïw@ç2Z ÿwl_18SWITCH_REG1ÿlcd_33pwm@20030000,rockchip,rk2928-pwm£ [ØF ódisabledËdefaultÙpwm@20030010,rockchip,rk2928-pwm£ [ØFóokayËdefaultÙwatchdog@2004c000 ,rockchip,rk3188-wdtsnps,dw-wdt£ ÀØK §3óokaypwm@20050020,rockchip,rk2928-pwm£  [ØGóokayËdefaultÙ pwm@20050030,rockchip,rk2928-pwm£ 0[ØGóokayËdefaultÙ!i2c@20056000,rockchip,rk3188-i2c£ ` §**ØRßi2c ódisabledËdefaultÙ"touchscreen@40,silead,gsl1680£@#§ fr …˜i2c@2005a000,rockchip,rk3188-i2c£   §+*ØSßi2c ódisabledËdefaultÙ$i2c@2005e000,rockchip,rk3188-i2c£ à §4*ØTßi2c ódisabledËdefaultÙ%serial@20064000&,rockchip,rk3188-uartsnps,dw-apb-uart£ @ §$´¾ßbaudclkapb_pclkØBNóokayËdefaultÙ&serial@20068000&,rockchip,rk3188-uartsnps,dw-apb-uart£ € §%´¾ßbaudclkapb_pclkØCOóokayËdefaultÙ'saradc@2006c000,rockchip,saradc£ À §«ØGJßsaradcapb_pclkOW dsaradc-apb ódisabledspi@20070000(,rockchip,rk3188-spirockchip,rk3066-spiØEHßspiclkapb_pclk §&£ J Otxrx ódisabledËdefaultÙ()*+spi@20074000(,rockchip,rk3188-spirockchip,rk3066-spiØFIßspiclkapb_pclk §'£ @J Otxrx ódisabledËdefaultÙ,-./cpus½rockchip,rk3066-smpcpu@0Ëcpu,arm,cortex-a9×0£èœ@Øö1O 2cpu@1Ëcpu,arm,cortex-a9×0£ö1O 2cpu@2Ëcpu,arm,cortex-a9×0£ö1O 2cpu@3Ëcpu,arm,cortex-a9×0£ö1O 2opp_table0,operating-points-v2ë1opp-312000000 ˜¾' Yø5œ@opp-504000000  n'Hopp-600000000 #ÃF'~ðFopp-816000000 0£,'à˜opp-1008000000 <Ü'g8opp-1200000000 G†Œ'Œ0opp-1416000000 Tfr'Ðopp-1608000000 _Ø"'™pdisplay-subsystem,rockchip,display-subsystemR34sram@10080000 ,mmio-sram£€ œ€smp-sram@0,rockchip,rk3066-smp-sram£Pvop@1010c000,rockchip,rk3188-vop£À § ØþÍßaclk_vopdclk_vophclk_vopfOdef daxiahbdclk ódisabledportë3vop@1010e000,rockchip,rk3188-vop£à §ØÄ¿Îßaclk_vopdclk_vophclk_vopfOghi daxiahbdclk ódisabledportë4timer@2000e000,,rockchip,rk3188-timerrockchip,rk3288-timer£ à  §.ØWE ßtimerpclktimer@200380a0,,rockchip,rk3188-timerrockchip,rk3288-timer£ €   §@ØZB ßtimerpclki2s@1011a000(,rockchip,rk3188-i2srockchip,rk3066-i2s£   § ËdefaultÙ5J66Otxrxßi2s_hclki2s_clkØÆKXs ódisabledsound@1011e000,,rockchip,rk3188-spdifrockchip,rk3066-spdif£à  ßhclkmclkØÅNJ6Otx § ËdefaultÙ7 ódisabledclock-controller@20000000,rockchip,rk3188-cru£ * žëefuse@20010000,rockchip,rk3188-efuse£ @Ø[ ßpclk_efusecpu_leakage@17£phy0,rockchip,rk3188-usb-phyrockchip,rk3288-usb-phy*óokayusb-phy@10c«£ ØQßphyclk ëusb-phy@11c«£ØRßphyclk ëpinctrl,rockchip,rk3188-pinctrl*¶8œgpio0@2000a000,rockchip,rk3188-gpio-bank0£   §6ØUÃÓŽ£ëgpio1@2003c000,rockchip,gpio-bank£ À §7ØVÃÓŽ£ë#gpio2@2003e000,rockchip,gpio-bank£ à §8ØWÃÓŽ£gpio3@20080000,rockchip,gpio-bank£  §9ØXÃÓŽ£pcfg_pull_upßë:pcfg_pull_downìpcfg_pull_noneûë9emmcemmc-clk9ëemmc-cmd:ëemmc-rst9ëemacemac-xfer€99999999emac-mdio 99i2c0i2c0-xfer 99ëi2c1i2c1-xfer 99ëi2c2i2c2-xfer 99ë"i2c3i2c3-xfer 99ë$i2c4i2c4-xfer 99ë%lcdc1lcdc1-dclk9lcdc1-den9lcdc1-hsync9lcdc1-vsync9ldcd1-rgb24€999999999 9 9 9 9 99999999999pwm0pwm0-out9ëpwm1pwm1-out9ëpwm2pwm2-out9ë pwm3pwm3-out9ë!spi0spi0-clk:ë(spi0-cs0:ë+spi0-tx:ë)spi0-rx:ë*spi0-cs1:spi1spi1-clk:ë,spi1-cs0:ë/spi1-rx:ë.spi1-tx:ë-spi1-cs1:uart0uart0-xfer :9ëuart0-cts9uart0-rts9uart1uart1-xfer :9ëuart1-cts9uart1-rts9uart2uart2-xfer : 9ë&uart3uart3-xfer  : 9ë'uart3-cts 9uart3-rts 9sd0sd0-clk9ë sd0-cmd9ë sd0-cd9ë sd0-wp 9sd0-pwr9sd0-bus-width19sd0-bus-width4@9999ë sd1sd1-clk9sd1-cmd9sd1-cd9sd1-wp9sd1-bus-width19sd1-bus-width4@9999i2s0i2s0-bus`999999ë5spdifspdif-tx9ë7pcfg-output-lowusbhost-vbus-drv9otg-vbus-drv9chosen!serial2:115200n8memory@60000000£`€Ëmemorygpio-keys ,gpio-keys-power l8tCGPIO Key PowerI;Zdvsys-regulator,regulator-fixedÿvsysÏLK@çLK@½ë #address-cells#size-cellsinterrupt-parentcompatiblemodelethernet0i2c0i2c1i2c2i2c3i2c4mshc0mshc1mshc2serial0serial1serial2serial3spi0spi1rangesreginterrupts#dma-cellsarm,pl330-broken-no-flushpclocksclock-namesphandlestatusclock-frequency#clock-cellsclock-output-namesassigned-clocksassigned-clock-ratesresetsinterrupt-namespower-domainscache-unifiedcache-levelinterrupt-controller#interrupt-cellsreg-shiftreg-io-widthpinctrl-namespinctrl-0dr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephysphy-namesrockchip,grfmax-speedphy-modedmasdma-namesfifo-depthreset-namesvmmc-supplybus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpnon-removableoffsetmode-normalmode-recoverymode-bootloadermode-loader#power-domain-cellspm_qosrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-nameregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvolt#pwm-cellspower-gpiostouchscreen-size-xtouchscreen-size-ysilead,max-fingers#io-channel-cellsenable-methoddevice_typenext-level-cacheclock-latencyoperating-points-v2cpu-supplyopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendportsrockchip,playback-channelsrockchip,capture-channels#sound-dai-cells#reset-cells#phy-cellsrockchip,pmugpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disablerockchip,pinsoutput-lowstdout-pathautorepeatlinux,codelabellinux,input-typedebounce-interval